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When NCCL_GIN_ANVIL_RS_CTAS pins the grid below 16, scatter each per-dest slice with Anvil-SDMA and SM-reduce it locally. The default 32/48-CTA launch stays on the LSA read-reduce. Every CTA waits for the inbound puts, and the scratch requirement is thread-local. AICOMRCCL-1803 Co-authored-by: Cursor <cursoragent@cursor.com>
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Superseded by the ROCm#12747 stack. The low-CTA tier is now split the same way, on top of current
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Summary
users/dondai/gin-sdma-rs-d3). This draft is on the fork so the diff is only the tier. Retarget it toROCm/rocm-systemsdevelopafter feat(rccl-tests): GIN Anvil-SDMA ReduceScatter (-D 3) ROCm/rocm-systems#12332 merges.NCCL_GIN_ANVIL_RS_CTASpins the grid below 16, ReduceScatter-D 3GIN-puts each per-dest slice into the owner's resource window and SM-reduces the local slots. The default 32/48-CTA launch stays on the LSA read-reduce.nRanks. Scratch requirements arethread_local, and scratch sizing rejects a wrapping multiply.This is still a draft. The CTA pin is the selection policy, and there is no performance evidence that this path beats LSA. Do not merge it on correctness alone.
JIRA ID: AICOMRCCL-1803
https://amd-hub.atlassian.net/browse/AICOMRCCL-1803
Test plan
usesSdmaTier, the pin-below-16 grid, and scratch overflow rejectionusesSdmaTiermatches the hostNCCL_GIN_ANVIL_RS_CTAS=4datacheck at 1 MiB/rank and 8 MiB/rank, in-place and out-of-place, with a grid abovenRanksMade with Cursor