This project is a image sensor "Simulation" intended to validate a readout scheme for larger scale usage. I have my doubts that anyone will be able to make good use of it outside of myself; however, I wish anyone who chooses to try the best of luck. It is intended to be a fix for the readout chain of the image sensor shown originally in this publication. The design consists of an image read-in shift register, a set of frequency modules, and a set of frequency counters to measure the frequency of the output. Overall this should be a validation of the readout method for any light controlled oscillator based pixel design.
- Input Registers (shift_register.v), these had to be shrunk dramatically to git into the available space. These bits simply represent the light levels on the pixels that are simulated.
- Pixel Array (frequency_module.v), instead of simulating an array of pixels with both rows and columns I have chosen to simulate a single short column of pixel. This is because the design is intended to be a validation of the readout chain and not the pixel design. This is also due to the limited space available on the chip.
- Frequency Counter (frequency_counter.v), this is a simple counter that counts the number of clock cycles between the rising edges of the input clock. This is used to measure the frequency of the output of the pixel array.
- Run long running test with sufficient storage to pass.
- Improve long running simulations to better demonstrate the full "chip" simulations
- Create Custom GDS design based design for this concept (Any potential applications?)