[Deepin-Kernel-SIG] [linux-6.6.y] [deepin] hwmon: (k10temp) Check return value of hygon_read_temp()

arch/arm64/kernel/acpi.c

@@ -269,6 +269,20 @@ pgprot_t __acpi_get_mem_attribute(phys_addr_t addr)
 
 void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
 {
+#ifdef CONFIG_ARM64
+       if (read_cpuid_implementor() == ARM_CPU_IMP_HISI) {
+               /* For normal memory we already have a cacheable mapping. */
+               if (memblock_is_map_memory(phys))
+	               return (void __iomem *)__phys_to_virt(phys);
+
+               /*
+               * We should still honor the memory's attribute here because
+               * crash dump kernel possibly excludes some ACPI (reclaim)
+               * regions from memblock list.
+               */
+               return ioremap_prot(phys, size, pgprot_val(__acpi_get_mem_attribute(phys)));
+       }
+#endif
 	efi_memory_desc_t *md, *region = NULL;
 	pgprot_t prot;
 

drivers/acpi/cppc_acpi.c

@@ -681,7 +681,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	acpi_status status;
 	int ret = -ENODATA;
 
+#ifdef CONFIG_ARM64
+	if (read_cpuid_implementor() != ARM_CPU_IMP_HISI && !osc_sb_cppc2_support_acked) {
+#else
 	if (!osc_sb_cppc2_support_acked) {
+#endif
 		pr_debug("CPPC v2 _OSC not acked\n");
 		if (!cpc_supported_by_cpu())
 			return -ENODEV;

drivers/hwmon/k10temp.c

@@ -208,21 +208,24 @@ static int k10temp_read_labels(struct device *dev,
 	return 0;
 }
 
-static void hygon_read_temp(struct k10temp_data *data, int channel,
+static int hygon_read_temp(struct k10temp_data *data, int channel,
 			       u32 *regval)
 {
 	struct hygon_private *h_priv;
+	int ret = -EOPNOTSUPP;
 
 	h_priv = (struct hygon_private *)data->priv;
 	if ((channel - 2) < h_priv->index_2nd)
-		amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
-			     ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
-					  regval);
+		ret = amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
+				   ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
+				   regval);
 	else
-		amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
-			     ZEN_CCD_TEMP(h_priv->offset_2nd,
-					  channel - 2 - h_priv->index_2nd),
-					  regval);
+		ret = amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
+				   ZEN_CCD_TEMP(h_priv->offset_2nd,
+				   channel - 2 - h_priv->index_2nd),
+				   regval);
+
+	return ret;
 }
 
 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
@@ -247,15 +250,14 @@ static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
 			break;
 		case 2 ... 13:		/* Tccd{1-12} */
 			if (hygon_f18h_m4h())
-				hygon_read_temp(data, channel, &regval);
+				ret = hygon_read_temp(data, channel, &regval);
 			else {
 				ret = amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 						   ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
 						   &regval);
-
-				if (ret)
-					return ret;
 			}
+			if (ret)
+				return ret;
 
 			*val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
 			break;
@@ -442,10 +444,21 @@ static void k10temp_get_ccd_support_2nd(struct pci_dev *pdev,
 
 	h_priv = (struct hygon_private *)data->priv;
 	for (i = h_priv->index_2nd; i < limit; i++) {
-		amd_smn_read(amd_pci_dev_to_node_id(pdev),
+               /*
+                * Ignore inaccessible CCDs.
+                *
+                * Some systems will return a register value of 0, and the TEMP_VALID
+                * bit check below will naturally fail.
+                *
+                * Other systems will return a PCI_ERROR_RESPONSE (0xFFFFFFFF) for
+                * the register value. And this will incorrectly pass the TEMP_VALID
+                * bit check.
+                */
+		if (amd_smn_read(amd_pci_dev_to_node_id(pdev),
 			     ZEN_CCD_TEMP(h_priv->offset_2nd,
 			     i - h_priv->index_2nd),
-			     &regval);
+			     &regval))
+			continue;
 		if (regval & ZEN_CCD_TEMP_VALID)
 			data->show_temp |= BIT(TCCD_BIT(i));
 	}