drm/arise:upgrade glenfly arise1 series GPU DRM kernel driver to V35

Signed-off-by: brightyi <[email protected]>

drivers/gpu/drm/arise/Makefile

@@ -1,12 +1,11 @@
 CHIP?=E3k
 DRIVER_NAME?=arise
-PRO_DRIVER_NAME=$(DRIVER_NAME)
 TARGET_ARCH?=x86_64
 DEBUG?=0
 VIDEO_ONLY_FPGA?=0
 RUN_HW_NULL?=0
 HW_NULL?=0
-CONFIG-GFGPU=m
+CONFIG_DRM_ARISE?=m
 ifeq ("$(M)", "")
 CHECK_GCC_VERSION?=0
 else
@@ -80,4 +79,4 @@ endif
 include $(GFGPU_FULL_PATH)/core/Makefile
 include $(GFGPU_FULL_PATH)/cbios/cbios.mk
 include $(GFGPU_FULL_PATH)/linux/Makefile
-obj-$(CONFIG_DRM_ARISE) := $(PRO_DRIVER_NAME).o
+obj-$(CONFIG_DRM_ARISE) := $(DRIVER_NAME).o

drivers/gpu/drm/arise/cbios/Device/CBiosShare.h

@@ -224,7 +224,7 @@ static inline CBIOS_U32 cb_swab32(CBIOS_U32 x)
 #define cbmemset(s1, v, n)     CBIOS_NULL
 #define cbmemcpy(s1, s2, n)    CBIOS_NULL
 #define cbmemcmp(s1, s2, n)    0
-#define cbdo_div(a, b)         0
+#define cbdo_div(a, b)   0
 #define cbvsprintf(s, f, ...)  0
 
 #else

drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosCRTMonitor.c

@@ -70,7 +70,7 @@ CBIOS_BOOL cbCRTMonitor_Detect(PCBIOS_VOID pvcbe, PCBIOS_CRT_MONITOR_CONTEXT pCr
         //then after resume,driver will not enter some hdmi module related codes,so monitor can't light
         //so not memset pDevCommon->EdidStruct when device is not connected
         cbClearEdidRelatedData(pcbe, pDevCommon);
-                
+
         if(cbDIU_CRT_DACSense(pcbe, pDevCommon, bPrevEdidValid))
         {
             pDevCommon->CurrentMonitorType = CBIOS_MONITOR_TYPE_CRT;

drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosHDMIMonitor.c

@@ -1449,7 +1449,7 @@ CBIOS_VOID cbHDMIMonitor_SetMode(PCBIOS_VOID pvcbe, PCBIOS_HDMI_MONITOR_CONTEXT
     if (bHDMIDevice)
     {
         // avoid HBlank being too small to not transmit any packet(32 bytes).
-        if (pModeParams->TargetTiming.HorBEnd - pModeParams->TargetTiming.HorBStart < 
+        if (pModeParams->TargetTiming.HorBEnd - pModeParams->TargetTiming.HorBStart <
             HDMI_DELAY_FOR_HDCP + HDMI_LEADING_GUARD_BAND_PERIOD + HDMI_MIN_CTL_PERIOD + HDMI_TRAILING_GUARD_BAND_PERIOD + 32)
         {
             bHDCPCapable = CBIOS_FALSE;

drivers/gpu/drm/arise/cbios/Display/CBiosDisplayManager.c

@@ -446,7 +446,7 @@ static CBIOS_STATUS cbDispMgrPrepareToSetMode(PCBIOS_EXTENSION_COMMON pcbe, PCBI
         bForceHDTV = CBIOS_TRUE;
     }
     cbPathMgrSelectDIUPath(pcbe, pDevCommon->DeviceType, pModeParams->IGAIndex, &pSettingModeParams->DestModeParams, bForceHDTV);
-    
+
     cbDevUpdateDeviceModeInfo(pcbe, pDevCommon, pModeParams);
 
     return csRet;

drivers/gpu/drm/arise/cbios/Display/CBiosMode.c

@@ -5667,6 +5667,14 @@ CBIOS_VOID cbMode_GetFilterPara(PCBIOS_VOID pvcbe, CBIOS_ACTIVE_TYPE Device, PCB
         break;
     }
 
+    if((pcbe->ChipID == CHIPID_ARISE2030) || (pcbe->ChipID == CHIPID_ARISE2020))
+    {
+        if((Device == CBIOS_TYPE_DP2) && (MonitorType == CBIOS_MONITOR_TYPE_HDMI))
+        {
+            pFilter->MaxDclk = 3400000;
+        }
+    }
+
     if(pFilter->MaxDclk > pcbe->ChipLimits.ulMaxIGAClock)
     {
         pFilter->MaxDclk = pcbe->ChipLimits.ulMaxIGAClock;

drivers/gpu/drm/arise/cbios/Display/CBiosPathManager.c

@@ -64,7 +64,7 @@ CBIOS_STATUS cbPathMgrGetDevComb(PCBIOS_VOID pvcbe, PCBIOS_GET_DEV_COMB pDevComb
     while(Devices)
     {
         bAssigned = CBIOS_FALSE;
-        
+
         //select a high priority device if more than one device
         TempDev = cbDevGetPrimaryDevice(Devices);
         Devices &= ~TempDev;
@@ -98,15 +98,15 @@ CBIOS_STATUS cbPathMgrGetDevComb(PCBIOS_VOID pvcbe, PCBIOS_GET_DEV_COMB pDevComb
         pDeviceComb->Iga3Dev = DevOnIga[IGA3];
         pDeviceComb->Iga4Dev = DevOnIga[IGA4];
         pDevComb->bSupported = CBIOS_TRUE;
-        
+
         return CBIOS_OK;
     }
     else
     {
         pDevComb->bSupported = CBIOS_FALSE;
         return CBIOS_ER_INVALID_PARAMETER;
     }
-    
+
 }
 
 CBIOS_STATUS cbPathMgrGetIgaMask(PCBIOS_VOID pvcbe, PCBIOS_GET_IGA_MASK pGetIgaMask)

drivers/gpu/drm/arise/cbios/Hw/Arise/CBios_Arise.c

@@ -689,6 +689,12 @@ CBIOS_VOID cbSetSRTimingReg_Arise(PCBIOS_EXTENSION_COMMON pcbe,
     {
         cbBiosMMIOWriteReg(pcbe, CR_8F, Value, (CBIOS_U8)~0xc0, IGAIndex);
     }
+
+    //Fix Arise1020/2030 VGA Hsync Timing issue
+    if(pcbe->DispMgr.ActiveDevices[IGAIndex] == CBIOS_TYPE_CRT)
+    {
+        cbMMIOWriteReg(pcbe, SR_18, 0x80, 0x7F);
+    }
 }
 
 

drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_CRT.c

@@ -33,7 +33,7 @@ static CBREGISTER NewCRTDetectEnv[] = {
     {SR,(CBIOS_U8)~0x01,0x0B, 0x00 },       //Turn on DCLK2
     {SR,(CBIOS_U8)~0x20,0x18, 0x20 },       //Turn on CRT Dac1
     {SR,(CBIOS_U8)~0x02,0x21, 0x02 },       //Turn on CRT Dac1 Sense power
-    {SR,(CBIOS_U8)~0x02,0x20, 0x00 },       //CRT DAC not off in Standby mode 
+    {SR,(CBIOS_U8)~0x02,0x20, 0x00 },       //CRT DAC not off in Standby mode
     {SR,(CBIOS_U8)~0x4C,0x31, 0x44 },       //DAC1 Sense Data Source Select
     {SR, 0x00,0x4B, 0x94 },        // R sense data
     {SR, 0x00,0x4C, 0x94 },        // G sense data
@@ -270,9 +270,9 @@ CBIOS_BOOL cbDIU_CRT_DACSense(PCBIOS_VOID pvcbe, PCBIOS_DEVICE_COMMON pDevCommon
     {
         return  (DacSensePara.Connected)? CBIOS_TRUE : CBIOS_FALSE;
     }
-    
+
     if(DacSensePara.UseNewSense)
-    {        
+    {
         //Use new DAC1 sense logic when CRT is on.
         RegSR21Value.Value = 0;
         RegSR21Value.DAC1_SENSE_Power_Down_Enable = 0;
@@ -301,11 +301,11 @@ CBIOS_BOOL cbDIU_CRT_DACSense(PCBIOS_VOID pvcbe, PCBIOS_DEVICE_COMMON pDevCommon
         RegCR71Mask.SENSEL = 0;
         RegCR71Mask.SENWIDTH = 0;
         cbMMIOWriteReg(pcbe,CR_71, RegCR71Value.Value, RegCR71Mask.Value);
-        
+
         cbMMIOWriteReg(pcbe,SR_4B, 0x7A, 0x00);   //R sense
         cbMMIOWriteReg(pcbe,SR_4C, 0x7A, 0x00);   // G sense
         cbMMIOWriteReg(pcbe,SR_4D, 0x7A, 0x00);  // B sense
-        
+
         RegSR3FValue.Value = 0;
         RegSR3FValue.B_Sense_1to0 = 3;
         RegSR3FValue.G_Sense_1to0 = 3;

drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosPHY_DP.c

@@ -1579,7 +1579,7 @@ static CBIOS_BOOL cbPHY_DP_SelectTMDSModeSource(PCBIOS_EXTENSION_COMMON pcbe, CB
             else if(MonitorType == CBIOS_MONITOR_TYPE_DVI)
             {
                 RegSR3AValue.Value = 0;
-                RegSR3AValue.DP_PHY_Source_Sel = 0;
+                RegSR3AValue.DP_PHY_Source_Sel = 4; //PS background overlay will affect DE of DVI timing, force to HDMI mode can fix this issue
             }
             RegSR3AMask.Value = 0xFF;
             RegSR3AMask.DP_PHY_Source_Sel = 0;

drivers/gpu/drm/arise/cbios/Hw/HwUtil/CBiosUtilHw.c

@@ -1236,11 +1236,18 @@ CBIOS_U32 cbGetProgClock(PCBIOS_EXTENSION_COMMON pcbe, CBIOS_U32 *ClockFreq, CBI
 {
     CBIOS_CLOCK_INFO ClkInfo = {0};
     CBIOS_U32 RegD130 = 0;
+    CBIOS_U32 D300_Value = 0;
+    CBIOS_BOOL bUseNewMclk = CBIOS_FALSE;
 
     if(ClockType >= CBIOS_INVALID_CLK)
     {
         return -1;
     }
+    if (pcbe->ChipID == CHIPID_ARISE1020 && ClockType == CBIOS_MCLKTYPE)
+    {
+        D300_Value = cb_ReadU32(pcbe->pAdapterContext, 0xD300);
+        bUseNewMclk = ((D300_Value & 0xF) == 0xA) ? CBIOS_TRUE : CBIOS_FALSE;
+    }
 
     switch (ClockType)
     {
@@ -1295,17 +1302,25 @@ CBIOS_U32 cbGetProgClock(PCBIOS_EXTENSION_COMMON pcbe, CBIOS_U32 *ClockFreq, CBI
         }
         break;
     case CBIOS_MCLKTYPE:
-        RegD130 = cb_ReadU32(pcbe->pAdapterContext, 0xd130);
-        ClkInfo.Integer = ((RegD130 >> 0x7) & 0x7F) | ((RegD130 & 0x10)? 0x80:0);
-        ClkInfo.R = (RegD130 >> 0x11) & 0x3;
-        ClkInfo.Fraction = 0;
-        ClkInfo.PLLDiv = 0;
+        if(bUseNewMclk)
+        {
+            *ClockFreq = (D300_Value & 0xFFF00)>>8;
+        }
+        else
+        {
+            RegD130 = cb_ReadU32(pcbe->pAdapterContext, 0xd130);
+            ClkInfo.Integer = ((RegD130 >> 0x7) & 0x7F) | ((RegD130 & 0x10)? 0x80:0);
+            ClkInfo.R = (RegD130 >> 0x11) & 0x3;
+            ClkInfo.Fraction = 0;
+            ClkInfo.PLLDiv = 0;
+        }
         break;
     default:
         break;
     }
 
-    if (pcbe->ChipID == CHIPID_ARISE10C0T && (ClockType == CBIOS_ECLKTYPE || ClockType == CBIOS_VCLKTYPE))
+    if ((pcbe->ChipID == CHIPID_ARISE10C0T && (ClockType == CBIOS_ECLKTYPE || ClockType == CBIOS_VCLKTYPE)) ||
+        (pcbe->ChipID == CHIPID_ARISE1020 && ClockType == CBIOS_MCLKTYPE && bUseNewMclk))
     {
         (*ClockFreq) *= 10000;
     }

drivers/gpu/drm/arise/cbios/cbios.mk

@@ -60,5 +60,5 @@ cbios-objs := \
     Hw/Arise/CBios_Arise.o          \
     Hw/Arise/CBiosVCP_Arise.o      
 
-$(PRO_DRIVER_NAME)-objs += $(addprefix cbios/, $(cbios-objs))
+$(DRIVER_NAME)-objs += $(addprefix cbios/, $(cbios-objs))
 

drivers/gpu/drm/arise/core/Makefile

@@ -58,7 +58,7 @@ core-objs := \
 	$(CORE_OBJ) \
 	$(PERF_EVENT_OBJ)
 
-$(PRO_DRIVER_NAME)-objs += $(addprefix core/, $(core-objs))
+$(DRIVER_NAME)-objs += $(addprefix core/, $(core-objs))
 
 ifeq ($(CHIP), E3k)
 	include $(GFGPU_FULL_PATH)/core/e3k/Makefile

drivers/gpu/drm/arise/core/e3k/Makefile

@@ -35,4 +35,4 @@ core_e3k-objs := \
     $(PERFEVENT_OBJ) \
 	$(GLOBAL_OBJ) 
 
-$(PRO_DRIVER_NAME)-objs += $(addprefix core/e3k/, $(core_e3k-objs))
+$(DRIVER_NAME)-objs += $(addprefix core/e3k/, $(core_e3k-objs))

drivers/gpu/drm/arise/gf_version.h

@@ -1,13 +1,13 @@
-#define DRIVER_DATE                 "07/15/2024"
+#define DRIVER_DATE                 "08/27/2024"
 #define DRIVER_MAJOR                0x25
 #define DRIVER_MINOR                0x00
-#define DRIVER_PATCHLEVEL           0x33
+#define DRIVER_PATCHLEVEL           0x35
 #define DRIVER_CLASS                ""
 #define DRIVER_NAME                 arise
 #define DRIVER_VENDOR               "Glenfly Tech Co., Ltd."
 #define DRIVER_LICENSE              "Glenfly"
 #define DRIVER_VERSION              ((DRIVER_MAJOR<<24)|(DRIVER_MINOR<<16)|DRIVER_PATCHLEVEL)
-#define DRIVER_VERSION_CHAR         "25.00.33"
+#define DRIVER_VERSION_CHAR         "25.00.35"
 #define OS_VERSION                  ""
 #define CC_VERSION                  ""
 #define LD_VERSION                  ""

drivers/gpu/drm/arise/linux/Makefile

@@ -55,4 +55,4 @@ else
 	linux-objs += gf_pcie.o
 endif
 
-$(PRO_DRIVER_NAME)-objs += $(addprefix linux/, $(linux-objs))
+$(DRIVER_NAME)-objs += $(addprefix linux/, $(linux-objs))

drivers/gpu/drm/arise/linux/gf.h

@@ -55,6 +55,8 @@
 #include <linux/log2.h>
 #include <linux/sysfs.h>
 #include <linux/device.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm.h>
 
 #ifndef DRM_VERSION_CODE
 #define DRM_VERSION_CODE LINUX_VERSION_CODE

drivers/gpu/drm/arise/linux/gf_atomic.c

@@ -16,6 +16,7 @@
 #include "gf_kms.h"
 #include "gf_sink.h"
 #include "gf_splice.h"
+#include "gf_pm.h"
 
 #if DRM_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)
 
@@ -245,6 +246,9 @@ static void gf_update_crtc_sink(struct drm_atomic_state *old_state)
 void gf_atomic_helper_commit_tail(struct drm_atomic_state *old_state)
 {
     struct drm_device *dev = old_state->dev;
+    struct drm_crtc *crtc;
+    struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+    int i;
 
 #if DRM_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)
     uint32_t flags = DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET;
@@ -256,7 +260,24 @@ void gf_atomic_helper_commit_tail(struct drm_atomic_state *old_state)
 
     drm_atomic_helper_commit_modeset_enables(dev, old_state);
 
-    gf_update_crtc_sink(old_state);
+#if DRM_VERSION_CODE < KERNEL_VERSION(4, 12, 0)
+    for_each_crtc_in_state(old_state, crtc, old_crtc_state, i)
+    {
+        new_crtc_state = crtc->state;
+#else
+    for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, new_crtc_state, i)
+    {
+#endif
+        if (old_crtc_state->active && !new_crtc_state->active)
+        {
+            gf_rpm_put_noidle(dev->dev);
+        }
+
+        if (new_crtc_state->active && !old_crtc_state->active)
+        {
+            gf_rpm_get_noresume(dev->dev);
+        }
+    }
 
     drm_atomic_helper_commit_planes(dev, old_state, flags);
 
@@ -275,6 +296,8 @@ void gf_atomic_helper_commit_tail(struct drm_atomic_state *old_state)
 #endif
 
     drm_atomic_helper_cleanup_planes(dev, old_state);
+
+    gf_rpm_mark_last_busy(dev->dev);
 }
 
 

drivers/gpu/drm/arise/linux/gf_cbios.h

@@ -16,8 +16,6 @@
 #define __GF_CBIOS_H__
 #include "CBios.h"
 
-#define MAX_CRTC_NUM CBIOS_MAX_CRTCS
-
 enum
 {
     FAMILY_CMODEL,

drivers/gpu/drm/arise/linux/gf_crtc.c

@@ -128,8 +128,6 @@ void  gf_crtc_helper_enable(struct drm_crtc *crtc)
     drm_crtc_vblank_on(crtc);
 
     gf_crtc_dpms_onoff_helper(crtc, 1);
-
-
 }
 
 #if DRM_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)

drivers/gpu/drm/arise/linux/gf_disp.c

@@ -73,6 +73,14 @@ static  char*  plane_name[] = {
     "FS",
 };
 
+static const unsigned int vsync_int_tbl[] = {
+    INT_VSYNC1,
+    INT_VSYNC2,
+    INT_VSYNC3,
+    INT_VSYNC4,
+};
+#define VSYNC_INT_TABLE_LEN (sizeof(vsync_int_tbl)/sizeof(vsync_int_tbl[0]))
+
 static char*  cursor_name = "cursor";
 
 #if  DRM_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)
@@ -672,6 +680,13 @@ static int  disp_crtc_init(disp_info_t* disp_info, unsigned int index)
     crtc_state->base_cstate.crtc = &gf_crtc->base_crtc;
     gf_crtc->crtc_dpms = 0;
 
+    if (index >= VSYNC_INT_TABLE_LEN)
+    {
+        gf_error("index excceds vsync int table length\n");
+        goto fail;
+    }
+    gf_crtc->vsync_int = vsync_int_tbl[index];
+
     gf_crtc->support_scale = disp_info->scale_support;
 
     gf_crtc->plane_cnt = disp_info->num_plane[index];
@@ -742,6 +757,13 @@ static int  disp_crtc_init(disp_info_t* disp_info, unsigned int index)
 
     gf_crtc->crtc_dpms = 0;
 
+    if (index >= VSYNC_INT_TABLE_LEN)
+    {
+        gf_error("index excceds vsync int table length\n");
+        goto fail;
+    }
+    gf_crtc->vsync_int = vsync_int_tbl[index];
+
     ret = drm_crtc_init(drm, &gf_crtc->base_crtc, &gf_crtc_funcs);
 
     if(ret)
@@ -1205,11 +1227,11 @@ static void disp_info_print(disp_info_t* disp_info)
     }
     if (DISP_OK == disp_cbios_get_clock(disp_info, GF_QUERY_ENGINE_CLOCK, &value))
     {
-        gf_info("displayinfo Eclk:%dMHz\n", value / 1000);
+        //gf_info("displayinfo Eclk:%dMHz\n", value / 1000);
     }
     if(DISP_OK == disp_cbios_get_clock(disp_info, GF_QUERY_VCLK, &value))
     {
-        gf_info("displayinfo Vclk:%dMHz\n", (value + 500)/1000);
+        //gf_info("displayinfo Vclk:%dMHz\n", (value + 500)/1000);
     }
     if(DISP_OK == disp_cbios_get_clock(disp_info, GF_QUERY_MCLK, &value))
     {