ui: split 'add_builtins' into 'add_vhdl_builtins' and 'add_verilog_bu…

…iltins'; remove vunit.verilog (VUnit#559)

examples/verilog/uart/run.py

@@ -15,11 +15,13 @@
 """
 
 from pathlib import Path
-from vunit.verilog import VUnit
+from vunit import VUnit
 
 SRC_PATH = Path(__file__).parent / "src"
 
 VU = VUnit.from_argv()
+VU.add_verilog_builtins()
+
 VU.add_library("uart_lib").add_source_files(SRC_PATH / "*.sv")
 VU.add_library("tb_uart_lib").add_source_files(SRC_PATH / "test" / "*.sv")
 

examples/verilog/user_guide/run.py

@@ -15,11 +15,13 @@
 """
 
 from pathlib import Path
-from vunit.verilog import VUnit
+from vunit import VUnit
 
 ROOT = Path(__file__).parent
 
 VU = VUnit.from_argv()
+VU.add_verilog_builtins()
+
 VU.add_library("lib").add_source_files(ROOT / "*.sv")
 
 VU.main()

examples/verilog/verilog_ams/run.py

@@ -7,11 +7,13 @@
 # Copyright (c) 2014-2021, Lars Asplund [email protected]
 
 from pathlib import Path
-from vunit.verilog import VUnit
+from vunit import VUnit
 
 ROOT = Path(__file__).parent
 
 VU = VUnit.from_argv()
+VU.add_verilog_builtins()
+
 LIB = VU.add_library("lib")
 LIB.add_source_files(ROOT / "*.sv")
 LIB.add_source_files(ROOT / "*.vams").set_compile_option("modelsim.vlog_flags", ["-ams"])

tests/acceptance/artificial/verilog/run.py

@@ -5,11 +5,14 @@
 # Copyright (c) 2014-2021, Lars Asplund [email protected]
 
 from pathlib import Path
-from vunit.verilog import VUnit
+from vunit import VUnit
+
 
 ROOT = Path(__file__).parent
 
 VU = VUnit.from_argv()
+VU.add_verilog_builtins()
+
 LIB = VU.add_library("lib")
 LIB.add_source_files(ROOT / "*.sv", defines={"DEFINE_FROM_RUN_PY": ""})
 

vunit/ui/__init__.py

@@ -157,7 +157,7 @@ def test_filter(name, attribute_names):
 
         self._builtins = Builtins(self, self._vhdl_standard, simulator_class)
         if compile_builtins:
-            self.add_builtins()
+            self.add_vhdl_builtins()
 
     def _create_database(self):
         """
@@ -925,9 +925,15 @@ def _run_test(self, test_cases, report):
         )
         runner.run(test_cases)
 
-    def add_builtins(self, external=None):
+    def add_verilog_builtins(self):
         """
-        Add vunit VHDL builtin libraries
+        Add VUnit Verilog builtin libraries
+        """
+        self._builtins.add_verilog_builtins()
+
+    def add_vhdl_builtins(self, external=None):
+        """
+        Add VUnit VHDL builtin libraries
 
         :param external: struct to provide bridges for the external VHDL API.
                          {

vunit/verilog/check/run.py

@@ -5,12 +5,14 @@
 # Copyright (c) 2014-2021, Lars Asplund [email protected]
 
 from pathlib import Path
-from vunit.verilog import VUnit
+from vunit import VUnit
 
 
 ROOT = Path(__file__).parent
 
 VU = VUnit.from_argv()
+VU.add_verilog_builtins()
+
 VU.add_library("lib").add_source_files(ROOT / "test" / "*.sv")
 VU.set_sim_option("modelsim.vsim_flags.gui", ["-novopt"])