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[RISC-V] Preliminary port to the riscv64 architecture #529

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cyring opened this issue Feb 22, 2025 · 3 comments
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[RISC-V] Preliminary port to the riscv64 architecture #529

cyring opened this issue Feb 22, 2025 · 3 comments
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cyring commented Feb 22, 2025 •
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Branch riscv64 portage is made on a QEMU Virtual Machine as described in this Gist
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cyring commented Feb 24, 2025

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@cyring cyring changed the title [RISC-V] Preliminary port of the riscv64 architecture [RISC-V] Preliminary port to the riscv64 architecture Feb 25, 2025
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cyring commented Feb 26, 2025

Commit 5c3bc58 brings a mean to read a TSC
We use the same instruction per Core and for the Package.
Base clock is now estimated dynamically,
but no register found for the factory clock which is still hard-coded to 1 GHz (as specified in QEMU)

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cyring commented Mar 8, 2025

  • mvendorid and marchid based architecture qualification in commit 450189f

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Repository owner locked and limited conversation to collaborators Mar 25, 2025
@cyring cyring converted this issue into discussion #537 Mar 25, 2025

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