[riscv64] Get the TSC from rdtime instruction

Author: cyring

riscv64/bitasm.h

@@ -85,22 +85,21 @@ __asm__ volatile							\
 )
 
 #define RDTSC64(_mem64) 						\
-/*TODO __asm__ volatile							\
+__asm__ volatile							\
 (									\
-	"csrr	%0	, mcycle"					\
+	"rdtime %0"							\
 	: "=r" (_mem64) 						\
 	:								\
 	: "cc", "memory"						\
-)*/									\
-	_mem64 = 0;
+)
 
 #define ASM_RDTSC(_reg) 						\
-	"# Read variant TSC."	/*TODO		"\n\t"			\
-	"csrr	" #_reg ",	mcycle" 	"\n\t"*/
+	"# Read variant TSC."			"\n\t"			\
+	"rdtime " #_reg 		 	"\n\t"
 
 #define ASM_CODE_RDPMC(_ctr, _reg)					\
 	"# Read PMU counter."			"\n\t"			\
-	"csrr	" #_reg ", " #_ctr		"\n\t"			\
+/*TODO	"csrr	" #_reg ", " #_ctr		"\n\t"	*/		\
 
 #define ASM_RDPMC(_ctr, _reg) ASM_CODE_RDPMC(_ctr, _reg)
 

riscv64/corefreqd.c

@@ -2033,16 +2033,16 @@ REASON_CODE Child_Manager(REF *Ref)
 			Arg[cpu].TID = 0;
 		}
 	} else {
-		unsigned int seed32 = time(0);
-/*TODO(Cycles)	__asm__ volatile
+		volatile unsigned long seed;
+		__asm__ volatile
 		(
-			"csrr %0, mcycle"
-			: "=r" (seed32)
+			"rdtime %0"
+			: "=r" (seed)
 			:
 			:
-		);*/
+		);
 	    #ifdef __GLIBC__
-		initstate_r(	seed32,
+		initstate_r(	(unsigned int) seed,
 				RO(Shm)->Cpu[cpu].Slice.Random.state,
 				sizeof(RO(Shm)->Cpu[cpu].Slice.Random.state),
 				&RO(Shm)->Cpu[cpu].Slice.Random.data );

riscv64/corefreqk.c

@@ -80,7 +80,7 @@ static signed int ArchID = -1;
 module_param(ArchID, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
 MODULE_PARM_DESC(ArchID, "Force an architecture (ID)");
 
-static signed int AutoClock = /*TODO: 0b11*/ 0b00;
+static signed int AutoClock = 0b11;
 module_param(AutoClock, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
 MODULE_PARM_DESC(AutoClock, "Estimate Clock Frequency 0:Spec; 1:Once; 2:Auto");
 
@@ -506,11 +506,13 @@ static signed int SearchArchitectureID(void)
 static void Query_Features(void *pArg)
 {
 	INIT_ARG *iArg = (INIT_ARG *) pArg;
-/*	volatile unsigned long long cntfrq;	TODO*/
+	volatile unsigned long long cntfrq;
 
 	iArg->Features->Info.Vendor.CRC = CRC_RESERVED;
 	iArg->SMT_Count = 1;
 	iArg->HypervisorID = HYPERV_NONE;
+
+	RDTSC64(cntfrq);
 /*TODO(Cycles)
 	__asm__ __volatile__(
 		"csrr	%[cntfrq],	mcycle" "\n\t"
@@ -539,14 +541,9 @@ static void Query_Features(void *pArg)
 #else
 	iArg->Features->ACPI = 0;
 #endif
-/*
 	iArg->Features->TSC = \
 	iArg->Features->Inv_TSC = \
 	iArg->Features->RDTSCP = cntfrq != 0;
-*/
-	iArg->Features->TSC = \
-	iArg->Features->Inv_TSC = \
-	iArg->Features->RDTSCP = 0;
 
 	iArg->Features->PerfMon.FixCtrs = \
 	iArg->Features->PerfMon.MonCtrs = \
@@ -1716,6 +1713,7 @@ static void Generic_Core_Counters_Clear(union SAVE_AREA_CORE *Save,
 
 #define Counters_Generic(Core, T)					\
 ({									\
+	RDTSC64(Core->Counter[T].TSC);					\
 /*TODO(Cycles)								\
 	RDTSC_COUNTERx3(Core->Counter[T].TSC,				\
 			pmevcntr2_el0:mcycle,	Core->Counter[T].C0.UCC,\
@@ -1818,7 +1816,8 @@ static void Generic_Core_Counters_Clear(union SAVE_AREA_CORE *Save,
 
 #define PKG_Counters_Generic(Core, T)					\
 ({									\
-/*TODO(Cycles)								\
+	RDTSC64(PUBLIC(RO(Proc))->Counter[T].PCLK);			\
+/*TODO(CleanUp)								\
 	volatile unsigned long long cntpct; 				\
 	__asm__ volatile						\
 	(								\

riscv64/corefreqm.c

@@ -50,12 +50,16 @@ void CallWith_RDTSC_RDPMC(	RO(SHM_STRUCT) *RO(Shm),
 				unsigned long arg )
 {
 	struct SLICE_STRUCT *pSlice = &RO(Shm)->Cpu[cpu].Slice;
+
+	RDTSC64(pSlice->Counter[0].TSC);
 /*TODO(Cycles)
 	RDTSC_PMCx1(	pSlice->Counter[0].TSC,
 			pmevcntr3_el0:mcycle,
 			pSlice->Counter[0].INST );
 */
 	pSlice->Counter[0].INST &= INST_COUNTER_OVERFLOW;
+
+	RDTSC64(pSlice->Counter[1].TSC);
 /*TODO(Cycles)
 	RDTSC_PMCx1(	pSlice->Counter[1].TSC,
 			pmevcntr3_el0:mcycle,
@@ -64,6 +68,8 @@ void CallWith_RDTSC_RDPMC(	RO(SHM_STRUCT) *RO(Shm),
 	pSlice->Counter[1].INST &= INST_COUNTER_OVERFLOW;
 
 	SliceFunc(RO(Shm), RW(Shm), cpu, arg);
+
+	RDTSC64(pSlice->Counter[2].TSC);
 /*TODO(Cycles)
 	RDTSC_PMCx1(	pSlice->Counter[2].TSC,
 			pmevcntr3_el0:mcycle,
@@ -122,7 +128,8 @@ void Slice_Atomic(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm),
 	UNUSED(RW(Shm));
 	register unsigned long loop = arg;
     do {
-/*	__asm__ volatile
+	__asm__ volatile("nop");
+/*TODO	__asm__ volatile
 	(
 		"ldr	x10,	%[_err]"		"\n\t"
 		"1:"					"\n\t"