[AArch64] Architectural Feature Access Control Register CPACR

aarch64/corefreq-api.h

@@ -206,6 +206,7 @@ typedef struct
 		Bit64			EL	__attribute__ ((aligned (8)));
 		Bit64			FPSR	__attribute__ ((aligned (8)));
 		Bit64			SVCR	__attribute__ ((aligned (8)));
+		Bit64			CPACR	__attribute__ ((aligned (8)));
 	} SystemRegister;
 
 	unsigned int			Bind;

aarch64/corefreq-cli-json.c

@@ -1414,6 +1414,11 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 			snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.SVCR);
 			json_key(&s, "SVCR");
 			json_string(&s, hexStr);
+
+			snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.CPACR);
+			json_key(&s, "CPACR");
+			json_string(&s, hexStr);
+
 			json_end_object(&s);
 		}
 		json_key(&s, "Slice");

aarch64/corefreq-cli-rsc-en.h

@@ -832,6 +832,17 @@
 #define RSC_SYS_REG_EL_EXEC_CODE_EN	" Executes in AArch64 or AArch32 "
 #define RSC_SYS_REG_EL_SEC_CODE_EN	" Secure Exception Level "
 
+#define RSC_SYS_REG_CPACR_CODE_EN	" Access Control Register "
+#define RSC_SYS_REG_ACR_TCP_CODE_EN	" Trap Coprocessor Access Control "
+#define RSC_SYS_REG_ACR_TAM_CODE_EN	" Trap Activity Monitor Access "
+#define RSC_SYS_REG_ACR_POE_CODE_EN	" Trap Permission Overlay Register EL0 "
+#define RSC_SYS_REG_ACR_TTA_CODE_EN	" Trap Trace unit Access "
+#define RSC_SYS_REG_ACR_SME_CODE_EN	" Trap SME, SVE instructions "
+#define RSC_SYS_REG_ACR_FP_CODE_EN	" Trap Advanced SIMD & Floating-Point "
+#define RSC_SYS_REG_ACR_ZEN_CODE_EN	" Trap SVE instructions ZCR Register "
+#define RSC_SYS_REG_ACR_R8_CODE_EN	" Reserved Bits [15:8] "
+#define RSC_SYS_REG_ACR_R0_CODE_EN	" Reserved Bits [7:0] "
+
 #define RSC_ISA_TITLE_CODE_EN		" Instruction Set Extensions "
 
 #define RSC_ISA_AES_COMM_CODE_EN	" Advanced Encryption Standard "
@@ -2073,6 +2084,9 @@
 	"Exec\0:   \0 64 \0 32 \0    \0 64 \0 32 \0    \0" \
 	" 64 \0 32 \0 SEC\0    \0 64 \0 32 "
 
+#define RSC_SYS_REG_HDR_CPACR_CODE	\
+	"ACR \0 TCP\0 TAM\0 POR\0 TTA\0 SME\0 FP \0 ZEN\0   R\0ES  "
+
 #define RSC_ISA_AES_CODE		"          AES [%c]"
 #define RSC_ISA_PMULL_CODE		"        PMULL [%c]"
 #define RSC_ISA_LSE_CODE		"          LSE [%c]"

aarch64/corefreq-cli-rsc-fr.h

@@ -524,6 +524,17 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_SYS_REG_EL_EXEC_CODE_FR	RSC_SYS_REG_EL_EXEC_CODE_EN
 #define RSC_SYS_REG_EL_SEC_CODE_FR	RSC_SYS_REG_EL_SEC_CODE_EN
 
+#define RSC_SYS_REG_CPACR_CODE_FR	RSC_SYS_REG_CPACR_CODE_EN
+#define RSC_SYS_REG_ACR_TCP_CODE_FR	RSC_SYS_REG_ACR_TCP_CODE_EN
+#define RSC_SYS_REG_ACR_TAM_CODE_FR	RSC_SYS_REG_ACR_TAM_CODE_EN
+#define RSC_SYS_REG_ACR_POE_CODE_FR	RSC_SYS_REG_ACR_POE_CODE_EN
+#define RSC_SYS_REG_ACR_TTA_CODE_FR	RSC_SYS_REG_ACR_TTA_CODE_EN
+#define RSC_SYS_REG_ACR_SME_CODE_FR	RSC_SYS_REG_ACR_SME_CODE_EN
+#define RSC_SYS_REG_ACR_FP_CODE_FR	RSC_SYS_REG_ACR_FP_CODE_EN
+#define RSC_SYS_REG_ACR_ZEN_CODE_FR	RSC_SYS_REG_ACR_ZEN_CODE_EN
+#define RSC_SYS_REG_ACR_R8_CODE_FR	RSC_SYS_REG_ACR_R8_CODE_EN
+#define RSC_SYS_REG_ACR_R0_CODE_FR	RSC_SYS_REG_ACR_R0_CODE_EN
+
 #define RSC_ISA_TITLE_CODE_FR		" Jeu d'instructions ""\xa9""tendu "
 
 #define RSC_ISA_AES_COMM_CODE_FR	RSC_ISA_AES_COMM_CODE_EN

aarch64/corefreq-cli-rsc.c

@@ -733,6 +733,17 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_SYS_REG_EL),
 	LDT(RSC_SYS_REG_EL_EXEC),
 	LDT(RSC_SYS_REG_EL_SEC),
+	LDQ(RSC_SYS_REG_HDR_CPACR),
+	LDT(RSC_SYS_REG_CPACR),
+	LDT(RSC_SYS_REG_ACR_TCP),
+	LDT(RSC_SYS_REG_ACR_TAM),
+	LDT(RSC_SYS_REG_ACR_POE),
+	LDT(RSC_SYS_REG_ACR_TTA),
+	LDT(RSC_SYS_REG_ACR_SME),
+	LDT(RSC_SYS_REG_ACR_FP),
+	LDT(RSC_SYS_REG_ACR_ZEN),
+	LDT(RSC_SYS_REG_ACR_R8),
+	LDT(RSC_SYS_REG_ACR_R0),
 	LDT(RSC_ISA_TITLE),
 	LDQ(RSC_ISA_AES),
 	LDT(RSC_ISA_AES_COMM),

aarch64/corefreq-cli-rsc.h

@@ -556,6 +556,17 @@ enum {
 	RSC_SYS_REG_EL,
 	RSC_SYS_REG_EL_EXEC,
 	RSC_SYS_REG_EL_SEC,
+	RSC_SYS_REG_HDR_CPACR,
+	RSC_SYS_REG_CPACR,
+	RSC_SYS_REG_ACR_TCP,
+	RSC_SYS_REG_ACR_TAM,
+	RSC_SYS_REG_ACR_POE,
+	RSC_SYS_REG_ACR_TTA,
+	RSC_SYS_REG_ACR_SME,
+	RSC_SYS_REG_ACR_FP,
+	RSC_SYS_REG_ACR_ZEN,
+	RSC_SYS_REG_ACR_R8,
+	RSC_SYS_REG_ACR_R0,
 	RSC_ISA_TITLE,
 	RSC_ISA_AES,
 	RSC_ISA_AES_COMM,

aarch64/corefreq-cli.c

@@ -453,7 +453,7 @@ REASON_CODE SystemRegisters(	Window *win,
 	};
 	enum AUTOMAT {
 		DO_END, DO_SPC, DO_CPU, DO_FLAG, DO_HCR,
-		DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR
+		DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR, DO_ACR
 	};
 	const struct SR_ST {
 		struct SR_HDR {
@@ -1061,6 +1061,48 @@ REASON_CODE SystemRegisters(	Window *win,
 	[16] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
 		{DO_END , 1	, UNDEF_CR	, 0	}
 	}
+      },
+      {
+	.header = (struct SR_HDR[]) {
+	[ 0] = {&RSC(SYS_REG_HDR_CPACR).CODE()[ 0],RSC(SYS_REG_CPACR).CODE()},
+	[ 1] = {&RSC(SYS_REG_HDR_CPACR).CODE()[ 5],RSC(SYS_REG_ACR_TCP).CODE()},
+	[ 2] = {&RSC(SYS_REG_HDR_CPACR).CODE()[10],RSC(SYS_REG_ACR_TAM).CODE()},
+	[ 3] = {&RSC(SYS_REG_HDR_CPACR).CODE()[15],RSC(SYS_REG_ACR_POE).CODE()},
+	[ 4] = {&RSC(SYS_REG_HDR_CPACR).CODE()[20],RSC(SYS_REG_ACR_TTA).CODE()},
+	[ 5] = {&RSC(SYS_REG_HDR_CPACR).CODE()[25],RSC(SYS_REG_ACR_SME).CODE()},
+	[ 6] = {&RSC(SYS_REG_HDR_CPACR).CODE()[30],RSC(SYS_REG_ACR_FP).CODE()},
+	[ 7] = {&RSC(SYS_REG_HDR_CPACR).CODE()[35],RSC(SYS_REG_ACR_ZEN).CODE()},
+	[ 8] = {&RSC(SYS_REG_HDR_CPACR).CODE()[40],RSC(SYS_REG_ACR_R8).CODE()},
+	[ 9] = {&RSC(SYS_REG_HDR_CPACR).CODE()[45],RSC(SYS_REG_ACR_R0).CODE()},
+	[10] = {RSC(SYS_REGS_SPACE).CODE(),	NULL},
+	[11] = {RSC(SYS_REGS_SPACE).CODE(),	NULL},
+	[12] = {RSC(SYS_REGS_SPACE).CODE(),	NULL},
+	[13] = {RSC(SYS_REGS_SPACE).CODE(),	NULL},
+	[14] = {RSC(SYS_REGS_SPACE).CODE(),	NULL},
+	[15] = {RSC(SYS_REGS_SPACE).CODE(),	NULL},
+	[16] = {RSC(SYS_REGS_SPACE).CODE(),	NULL},
+		{NULL, NULL}
+	},
+	.flag = (struct SR_BIT[]) {
+	[ 0] =	{DO_CPU , 1	, UNDEF_CR	, 0	},
+	[ 1] =	{DO_ACR , 1	, ACR_TCPAC	, 1	},
+	[ 2] =	{DO_ACR , 1	, ACR_TAM 	, 1	},
+	[ 3] =	{DO_ACR , 1	, ACR_E0POE	, 1	},
+	[ 4] =	{DO_ACR , 1	, ACR_TTA 	, 1	},
+	[ 5] =	{DO_ACR , 1	, ACR_SMEN	, 2	},
+	[ 6] =	{DO_ACR , 1	, ACR_FPEN	, 2	},
+	[ 7] =	{DO_ACR , 1	, ACR_ZEN 	, 2	},
+	[ 8] =	{DO_ACR , 1	, ACR_RES8	, 8	},
+	[ 9] =	{DO_ACR , 1	, ACR_RES0	, 8	},
+	[10] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
+	[11] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
+	[12] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
+	[13] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
+	[14] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
+	[15] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
+	[16] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
+		{DO_END , 1	, UNDEF_CR	, 0	}
+	}
       }
     };
 	CUINT cells_per_line = win->matrix.size.wth, *nl = &cells_per_line;
@@ -1135,6 +1177,11 @@ REASON_CODE SystemRegisters(	Window *win,
 			  BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.FPSR,
 					pFlag->pos, pFlag->len));
 			break;
+		    case DO_ACR:
+			PRT(REG, attrib[2], "%3llx ",
+			  BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.CPACR,
+					pFlag->pos, pFlag->len));
+			break;
 		    default:
 			PRT(REG, attrib[1], RSC(SYS_REGS_NA).CODE());
 			break;

aarch64/corefreq.h

@@ -193,6 +193,7 @@ typedef struct
 		Bit64			EL	__attribute__ ((aligned (8)));
 		Bit64			FPSR	__attribute__ ((aligned (8)));
 		Bit64			SVCR	__attribute__ ((aligned (8)));
+		Bit64			CPACR	__attribute__ ((aligned (8)));
 	} SystemRegister;
 
 	struct SLICE_STRUCT {

aarch64/corefreqd.c

@@ -878,6 +878,9 @@ void SystemRegisters(	RO(SHM_STRUCT) *RO(Shm), RO(CORE) **RO(Core),
 	RO(Shm)->Cpu[cpu].SystemRegister.SVCR = \
 				RO(Core, AT(cpu))->SystemRegister.SVCR;
 
+	RO(Shm)->Cpu[cpu].SystemRegister.CPACR = \
+				RO(Core, AT(cpu))->SystemRegister.CPACR;
+
 	RO(Shm)->Cpu[cpu].Query.SCTLRX = RO(Core, AT(cpu))->Query.SCTLRX;
 }
 

aarch64/corefreqk.c

@@ -2604,6 +2604,12 @@ static void SystemRegisters(CORE_RO *Core)
 			: "cc", "memory"
 		);
 	}
+	__asm__ __volatile__(
+		"mrs	%[cpacr],	cpacr_el1"
+		: [cpacr] 	"=r" (Core->SystemRegister.CPACR)
+		:
+		: "cc", "memory"
+	);
 	BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask, Core->Bind);
 }
 

aarch64/coretypes.h

@@ -289,6 +289,16 @@ enum SYS_REG {
 	FPSR_DZC	= 1,
 	FPSR_IOC	= 0,
 
+	ACR_TCPAC	= 31,
+	ACR_TAM 	= 30,
+	ACR_E0POE	= 29,
+	ACR_TTA 	= 28,
+	ACR_SMEN	= 24,	/* [25:24]				*/
+	ACR_FPEN	= 20,	/* [21:20]				*/
+	ACR_ZEN 	= 16,	/* [17:16]				*/
+	ACR_RES8	= 8,	/* [15: 8]				*/
+	ACR_RES0	= 0,	/* [ 7: 0]				*/
+
 	UNDEF_CR	= 64
 };