[AArch64] Display FP and SIMD bits from MVFR

* Added remaining `CLRBHB` and `PCDPHINT` of `ISAR2`
cyring · Dec 4, 2024 · d73f4dc · d73f4dc
1 parent 0ee6ea9
commit d73f4dc
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Showing 8 changed files with 271 additions and 37 deletions.
diff --git a/aarch64/arm_reg.h b/aarch64/arm_reg.h
@@ -445,7 +445,8 @@ typedef union
 		CLRBHB		: 32-28,
 		SYSREG_128	: 36-32,
 		SYSINSTR_128	: 40-36,
-		PRFMSLC 	: 48-40,
+		PRFMSLC 	: 44-40,
+		PCDPHINT	: 48-44,
 		RPRFM		: 52-48,
 		CSSC		: 56-52,
 		LUT		: 60-56,

diff --git a/aarch64/corefreq-cli-rsc-en.h b/aarch64/corefreq-cli-rsc-en.h
@@ -893,12 +893,14 @@
 #define RSC_ISA_PAUTH_COMM_CODE_EN	" Pointer Authentication "
 #define RSC_ISA_PAUTH2_COMM_CODE_EN	" Enhanced Pointer Authentication "
 #define RSC_ISA_PAUTH_LR_COMM_CODE_EN	" Pointer Authentication Link Register "
+#define RSC_ISA_PCDPHINT_COMM_CODE_EN " Producer-Consumer Data Placement Hints "
 #define RSC_ISA_PRFMSLC_COMM_CODE_EN	" PRFM instructions support SLC target "
 #define RSC_ISA_FRINTTS_COMM_CODE_EN	" Floating-point to Integer "
 #define RSC_ISA_SPECRES_COMM_CODE_EN	" Prediction Invalidation "
 #define RSC_ISA_ATS1A_COMM_CODE_EN	" Address Translation Stage 1 "
 #define RSC_ISA_BF16_COMM_CODE_EN	" BFloat16 instructions "
 #define RSC_ISA_EBF16_COMM_CODE_EN	" Extended BFloat16 "
+#define RSC_ISA_CLRBHB_COMM_CODE_EN	" Clear Branch History instruction "
 #define RSC_ISA_CONSTPACFLD_COMM_CODE_EN \
 					" Determine the size of the PAC Field "
 
@@ -2127,13 +2129,15 @@
 #define RSC_ISA_PAUTH_CODE		"        PAuth [%c]"
 #define RSC_ISA_PAUTH2_CODE		"       PAuth2 [%c]"
 #define RSC_ISA_PAUTH_LR_CODE		"     PAuth_LR [%c]"
+#define RSC_ISA_PCDPHINT_CODE		"     PCDPHINT [%c]"
 #define RSC_ISA_PRFMSLC_CODE		"      PRFMSLC [%c]"
 #define RSC_ISA_FRINTTS_CODE		"      FRINTTS [%c]"
 #define RSC_ISA_SPECRES_CODE		"      SPECRES [%c]"
 #define RSC_ISA_SPECRES2_CODE		"     SPECRES2 [%c]"
 #define RSC_ISA_ATS1A_CODE		"        ATS1A [%c]"
 #define RSC_ISA_BF16_CODE		"         BF16 [%c]"
 #define RSC_ISA_EBF16_CODE		"        EBF16 [%c]"
+#define RSC_ISA_CLRBHB_CODE		"       CLRBHB [%c]"
 #define RSC_ISA_CONSTPACFLD_CODE	"  CONSTPACFLD [%c]"
 #define RSC_ISA_CSSC_CODE		"         CSSC [%c]"
 #define RSC_ISA_HBC_CODE		"          HBC [%c]"
@@ -2195,3 +2199,21 @@
 #define RSC_ISA_SME_SF8DP2_CODE 	"   SME_SF8DP2 [%c]"
 #define RSC_ISA_FlagM_CODE		"        FlagM [%c]"
 #define RSC_ISA_FlagM2_CODE		"       FlagM2 [%c]"
+#define RSC_ISA_FP_ROUND_CODE		"     FP_ROUND [%c]"
+#define RSC_ISA_FP_SH_VEC_CODE		"    FP_Sh_Vec [%c]"
+#define RSC_ISA_FP_SQRT_CODE		"      FP_SQRT [%c]"
+#define RSC_ISA_FP_DIVIDE_CODE		"    FP_DIVIDE [%c]"
+#define RSC_ISA_FP_TRAP_CODE		"      FP_TRAP [%c]"
+#define RSC_ISA_FP_DP_CODE		"        FP_DP [%c]"
+#define RSC_ISA_FP_SP_CODE		"        FP_SP [%c]"
+#define RSC_ISA_FP_HP_CODE		"        FP_HP [%c]"
+#define RSC_ISA_FP_NaN_CODE		"       FP_NaN [%c]"
+#define RSC_ISA_FP_FtZ_CODE		"       FP_FtZ [%c]"
+#define RSC_ISA_FP_MISC_CODE 		"      FP_MISC [%c]"
+#define RSC_ISA_SIMD_REG_CODE		"     SIMD_REG [%c]"
+#define RSC_ISA_SIMD_FMA_CODE		"     SIMD_FMA [%c]"
+#define RSC_ISA_SIMD_HP_CODE		"      SIMD_HP [%c]"
+#define RSC_ISA_SIMD_SP_CODE		"      SIMD_SP [%c]"
+#define RSC_ISA_SIMD_INT_CODE		"     SIMD_INT [%c]"
+#define RSC_ISA_SIMD_LS_CODE		"      SIMD_LS [%c]"
+#define RSC_ISA_SIMD_MISC_CODE		"    SIMD_MISC [%c]"
diff --git a/aarch64/corefreq-cli-rsc-fr.h b/aarch64/corefreq-cli-rsc-fr.h
@@ -568,12 +568,14 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_ISA_PAUTH_COMM_CODE_FR	RSC_ISA_PAUTH_COMM_CODE_EN
 #define RSC_ISA_PAUTH2_COMM_CODE_FR	RSC_ISA_PAUTH2_COMM_CODE_EN
 #define RSC_ISA_PAUTH_LR_COMM_CODE_FR	RSC_ISA_PAUTH_LR_COMM_CODE_EN
+#define RSC_ISA_PCDPHINT_COMM_CODE_FR	RSC_ISA_PCDPHINT_COMM_CODE_EN
 #define RSC_ISA_PRFMSLC_COMM_CODE_FR	RSC_ISA_PRFMSLC_COMM_CODE_EN
 #define RSC_ISA_FRINTTS_COMM_CODE_FR	RSC_ISA_FRINTTS_COMM_CODE_EN
 #define RSC_ISA_SPECRES_COMM_CODE_FR	RSC_ISA_SPECRES_COMM_CODE_EN
 #define RSC_ISA_ATS1A_COMM_CODE_FR	RSC_ISA_ATS1A_COMM_CODE_EN
 #define RSC_ISA_BF16_COMM_CODE_FR	RSC_ISA_BF16_COMM_CODE_EN
 #define RSC_ISA_EBF16_COMM_CODE_FR	RSC_ISA_EBF16_COMM_CODE_EN
+#define RSC_ISA_CLRBHB_COMM_CODE_FR	RSC_ISA_CLRBHB_COMM_CODE_EN
 #define RSC_ISA_CONSTPACFLD_COMM_CODE_FR RSC_ISA_CONSTPACFLD_COMM_CODE_EN
 #define RSC_ISA_CSSC_COMM_CODE_FR	RSC_ISA_CSSC_COMM_CODE_EN
 #define RSC_ISA_HBC_COMM_CODE_FR	RSC_ISA_HBC_COMM_CODE_EN

diff --git a/aarch64/corefreq-cli-rsc.c b/aarch64/corefreq-cli-rsc.c
@@ -800,6 +800,8 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_ISA_PAUTH2_COMM),
 	LDQ(RSC_ISA_PAUTH_LR),
 	LDT(RSC_ISA_PAUTH_LR_COMM),
+	LDQ(RSC_ISA_PCDPHINT),
+	LDT(RSC_ISA_PCDPHINT_COMM),
 	LDQ(RSC_ISA_PRFMSLC),
 	LDT(RSC_ISA_PRFMSLC_COMM),
 	LDQ(RSC_ISA_FRINTTS),
@@ -813,6 +815,8 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_ISA_BF16_COMM),
 	LDQ(RSC_ISA_EBF16),
 	LDT(RSC_ISA_EBF16_COMM),
+	LDQ(RSC_ISA_CLRBHB),
+	LDT(RSC_ISA_CLRBHB_COMM),
 	LDQ(RSC_ISA_CONSTPACFLD),
 	LDT(RSC_ISA_CONSTPACFLD_COMM),
 	LDQ(RSC_ISA_CSSC),
@@ -897,6 +901,24 @@ RESOURCE_ST Resource[] = {
 	LDQ(RSC_ISA_FlagM),
 	LDT(RSC_ISA_FlagM_COMM),
 	LDQ(RSC_ISA_FlagM2),
+	LDQ(RSC_ISA_FP_ROUND),
+	LDQ(RSC_ISA_FP_SH_VEC),
+	LDQ(RSC_ISA_FP_SQRT),
+	LDQ(RSC_ISA_FP_DIVIDE),
+	LDQ(RSC_ISA_FP_TRAP),
+	LDQ(RSC_ISA_FP_DP),
+	LDQ(RSC_ISA_FP_SP),
+	LDQ(RSC_ISA_FP_HP),
+	LDQ(RSC_ISA_FP_NaN),
+	LDQ(RSC_ISA_FP_FtZ),
+	LDQ(RSC_ISA_FP_MISC),
+	LDQ(RSC_ISA_SIMD_REG),
+	LDQ(RSC_ISA_SIMD_FMA),
+	LDQ(RSC_ISA_SIMD_HP),
+	LDQ(RSC_ISA_SIMD_SP),
+	LDQ(RSC_ISA_SIMD_INT),
+	LDQ(RSC_ISA_SIMD_LS),
+	LDQ(RSC_ISA_SIMD_MISC),
 	LDT(RSC_FEATURES_TITLE),
 	LDT(RSC_ON),
 	LDT(RSC_OFF),

diff --git a/aarch64/corefreq-cli-rsc.h b/aarch64/corefreq-cli-rsc.h
@@ -623,6 +623,8 @@ enum {
 	RSC_ISA_PAUTH2_COMM,
 	RSC_ISA_PAUTH_LR,
 	RSC_ISA_PAUTH_LR_COMM,
+	RSC_ISA_PCDPHINT,
+	RSC_ISA_PCDPHINT_COMM,
 	RSC_ISA_PRFMSLC,
 	RSC_ISA_PRFMSLC_COMM,
 	RSC_ISA_FRINTTS,
@@ -636,6 +638,8 @@ enum {
 	RSC_ISA_BF16_COMM,
 	RSC_ISA_EBF16,
 	RSC_ISA_EBF16_COMM,
+	RSC_ISA_CLRBHB,
+	RSC_ISA_CLRBHB_COMM,
 	RSC_ISA_CONSTPACFLD,
 	RSC_ISA_CONSTPACFLD_COMM,
 	RSC_ISA_CSSC,
@@ -720,6 +724,24 @@ enum {
 	RSC_ISA_FlagM,
 	RSC_ISA_FlagM_COMM,
 	RSC_ISA_FlagM2,
+	RSC_ISA_FP_ROUND,
+	RSC_ISA_FP_SH_VEC,
+	RSC_ISA_FP_SQRT,
+	RSC_ISA_FP_DIVIDE,
+	RSC_ISA_FP_TRAP,
+	RSC_ISA_FP_DP,
+	RSC_ISA_FP_SP,
+	RSC_ISA_FP_HP,
+	RSC_ISA_FP_NaN,
+	RSC_ISA_FP_FtZ,
+	RSC_ISA_FP_MISC,
+	RSC_ISA_SIMD_REG,
+	RSC_ISA_SIMD_FMA,
+	RSC_ISA_SIMD_HP,
+	RSC_ISA_SIMD_SP,
+	RSC_ISA_SIMD_INT,
+	RSC_ISA_SIMD_LS,
+	RSC_ISA_SIMD_MISC,
 	RSC_FEATURES_TITLE,
 	RSC_ON,
 	RSC_OFF,