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[AArch64] Provides the 64 or 32 architecture execution per EL
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* Postpones `cpacr_el1` register
* Completes JSON with system registers
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@cyring
cyring committed Feb 6, 2024
1 parent faef876 commit d4e7a2c
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Showing 12 changed files with 169 additions and 7 deletions.
14 changes: 12 additions & 2 deletions aarch64/arm_reg.h
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Expand Up @@ -576,7 +576,7 @@ typedef union
struct
{
unsigned long long
EL0 : 4-0,
EL0 : 4-0, /*0b0001=AArch64;0b0010=AArch{32,64}*/
EL1 : 8-4,
EL2 : 12-8,
EL3 : 16-12,
Expand All @@ -594,7 +594,17 @@ typedef union
CSV3 : 64-60;
};
} AA64PFR0;

/*
CPU:AA64PFR0
1:0x0000000011112222
0:0x0000000011112222
2:0x0000000011112222
3:0x0000000011112222
4:0x1100000011111112
5:0x1100000011111112
6:0x1100000011111112
7:0x1100000011111112
*/
typedef union
{
unsigned long long value; /* Pkg:0x00000010 */
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1 change: 1 addition & 0 deletions aarch64/corefreq-api.h
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Expand Up @@ -199,6 +199,7 @@ typedef struct
Bit64 FLAGS __attribute__ ((aligned (8)));
Bit64 SCTLR __attribute__ ((aligned (8)));
Bit64 SCTLR2 __attribute__ ((aligned (8)));
Bit64 EL __attribute__ ((aligned (8)));
Bit64 FPSR __attribute__ ((aligned (8)));
Bit64 SVCR __attribute__ ((aligned (8)));
} SystemRegister;
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12 changes: 12 additions & 0 deletions aarch64/corefreq-cli-json.c
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Expand Up @@ -1316,6 +1316,18 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.SCTLR2);
json_key(&s, "SCTLR2");
json_string(&s, hexStr);

snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.EL);
json_key(&s, "EL");
json_string(&s, hexStr);

snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.FPSR);
json_key(&s, "FPSR");
json_string(&s, hexStr);

snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.SVCR);
json_key(&s, "SVCR");
json_string(&s, hexStr);
json_end_object(&s);
}
json_key(&s, "Slice");
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12 changes: 12 additions & 0 deletions aarch64/corefreq-cli-rsc-en.h
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Expand Up @@ -769,6 +769,10 @@
#define RSC_SYS_REG_FPSR_DZC_CODE_EN " Divide by Zero Cumulative "
#define RSC_SYS_REG_FPSR_IOC_CODE_EN " Invalid Operation Cumulative "

#define RSC_SYS_REG_EL_CODE_EN " Exception Level "
#define RSC_SYS_REG_EL_EXEC_CODE_EN " Executes in AArch64 or AArch32 "
#define RSC_SYS_REG_EL_SEC_CODE_EN " Secure Exception Level "

#define RSC_ISA_TITLE_CODE_EN " Instruction Set Extensions "

#define RSC_ISA_AES_COMM_CODE_EN " Advanced Encryption Standard "
Expand Down Expand Up @@ -1953,6 +1957,14 @@
#define RSC_SYS_REG_HDR_FPSR_CODE \
"FPSR\0 N \0 Z \0 C \0 V \0 QC \0 IDC\0 IXC\0 UFC\0 OFC\0 DZC\0 IOC"

#define RSC_SYS_REG_HDR11_EL_CODE \
" EL \0 \0"" Lev\0el0 \0 \0 Lev\0el1 \0 \0" \
" L\0evel\0""2 \0 \0 Lev\0el3 "

#define RSC_SYS_REG_HDR12_EL_CODE \
"Exec\0: \0 64 \0 32 \0 \0 64 \0 32 \0 \0" \
" 64 \0 32 \0 SEC\0 \0 64 \0 32 "

#define RSC_ISA_AES_CODE " AES [%c]"
#define RSC_ISA_PMULL_CODE " PMULL [%c]"
#define RSC_ISA_LSE_CODE " LSE [%c]"
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4 changes: 4 additions & 0 deletions aarch64/corefreq-cli-rsc-fr.h
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Expand Up @@ -461,6 +461,10 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_SYS_REG_FPSR_DZC_CODE_FR RSC_SYS_REG_FPSR_DZC_CODE_EN
#define RSC_SYS_REG_FPSR_IOC_CODE_FR RSC_SYS_REG_FPSR_IOC_CODE_EN

#define RSC_SYS_REG_EL_CODE_FR RSC_SYS_REG_EL_CODE_EN
#define RSC_SYS_REG_EL_EXEC_CODE_FR RSC_SYS_REG_EL_EXEC_CODE_EN
#define RSC_SYS_REG_EL_SEC_CODE_FR RSC_SYS_REG_EL_SEC_CODE_EN

#define RSC_ISA_TITLE_CODE_FR " Jeu d'instructions ""\xa9""tendu "

#define RSC_ISA_AES_COMM_CODE_FR RSC_ISA_AES_COMM_CODE_EN
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5 changes: 5 additions & 0 deletions aarch64/corefreq-cli-rsc.c
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Expand Up @@ -663,6 +663,11 @@ RESOURCE_ST Resource[] = {
LDT(RSC_SYS_REG_FPSR_OFC),
LDT(RSC_SYS_REG_FPSR_DZC),
LDT(RSC_SYS_REG_FPSR_IOC),
LDQ(RSC_SYS_REG_HDR11_EL),
LDQ(RSC_SYS_REG_HDR12_EL),
LDT(RSC_SYS_REG_EL),
LDT(RSC_SYS_REG_EL_EXEC),
LDT(RSC_SYS_REG_EL_SEC),
LDT(RSC_ISA_TITLE),
LDQ(RSC_ISA_AES),
LDT(RSC_ISA_AES_COMM),
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5 changes: 5 additions & 0 deletions aarch64/corefreq-cli-rsc.h
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Expand Up @@ -486,6 +486,11 @@ enum {
RSC_SYS_REG_FPSR_OFC,
RSC_SYS_REG_FPSR_DZC,
RSC_SYS_REG_FPSR_IOC,
RSC_SYS_REG_HDR11_EL,
RSC_SYS_REG_HDR12_EL,
RSC_SYS_REG_EL,
RSC_SYS_REG_EL_EXEC,
RSC_SYS_REG_EL_SEC,
RSC_ISA_TITLE,
RSC_ISA_AES,
RSC_ISA_AES_COMM,
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67 changes: 66 additions & 1 deletion aarch64/corefreq-cli.c
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Expand Up @@ -429,7 +429,7 @@ REASON_CODE SystemRegisters( Window *win,
};
enum AUTOMAT {
DO_END, DO_SPC, DO_CPU, DO_FLAG,
DO_SCTLR, DO_SCTLR2, DO_FPSR
DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR
};
const struct SR_ST {
struct SR_HDR {
Expand Down Expand Up @@ -750,6 +750,66 @@ REASON_CODE SystemRegisters( Window *win,
{DO_END , 1 , UNDEF_CR , 0 }
}
},
{
.header = (struct SR_HDR[]) {
[ 0] = {&RSC(SYS_REG_HDR11_EL).CODE()[ 0], RSC(SYS_REG_EL).CODE()},
[ 1] = {&RSC(SYS_REG_HDR11_EL).CODE()[ 5], NULL},
[ 2] = {&RSC(SYS_REG_HDR11_EL).CODE()[10], NULL},
[ 3] = {&RSC(SYS_REG_HDR11_EL).CODE()[15], NULL},
[ 4] = {&RSC(SYS_REG_HDR11_EL).CODE()[20], NULL},
[ 5] = {&RSC(SYS_REG_HDR11_EL).CODE()[25], NULL},
[ 6] = {&RSC(SYS_REG_HDR11_EL).CODE()[30], NULL},
[ 7] = {&RSC(SYS_REG_HDR11_EL).CODE()[35], NULL},
[ 8] = {&RSC(SYS_REG_HDR11_EL).CODE()[40], NULL},
[ 9] = {&RSC(SYS_REG_HDR11_EL).CODE()[45], NULL},
[10] = {&RSC(SYS_REG_HDR11_EL).CODE()[50], NULL},
[11] = {&RSC(SYS_REG_HDR11_EL).CODE()[55], NULL},
[12] = {&RSC(SYS_REG_HDR11_EL).CODE()[60], NULL},
[13] = {&RSC(SYS_REG_HDR11_EL).CODE()[65], NULL},
[14] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[15] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[16] = {RSC(SYS_REGS_SPACE).CODE(), NULL},

[17] = {&RSC(SYS_REG_HDR12_EL).CODE()[ 0], RSC(SYS_REG_EL_EXEC).CODE()},
[18] = {&RSC(SYS_REG_HDR12_EL).CODE()[ 5], NULL},
[19] = {&RSC(SYS_REG_HDR12_EL).CODE()[10], NULL},
[20] = {&RSC(SYS_REG_HDR12_EL).CODE()[15], NULL},
[21] = {&RSC(SYS_REG_HDR12_EL).CODE()[20], NULL},
[22] = {&RSC(SYS_REG_HDR12_EL).CODE()[25], NULL},
[23] = {&RSC(SYS_REG_HDR12_EL).CODE()[30], NULL},
[24] = {&RSC(SYS_REG_HDR12_EL).CODE()[35], NULL},
[25] = {&RSC(SYS_REG_HDR12_EL).CODE()[40], NULL},
[26] = {&RSC(SYS_REG_HDR12_EL).CODE()[45], NULL},
[27] = {&RSC(SYS_REG_HDR12_EL).CODE()[50], RSC(SYS_REG_EL_SEC).CODE()},
[28] = {&RSC(SYS_REG_HDR12_EL).CODE()[55], NULL},
[29] = {&RSC(SYS_REG_HDR12_EL).CODE()[60], NULL},
[30] = {&RSC(SYS_REG_HDR12_EL).CODE()[65], NULL},
[31] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[32] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[33] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
{NULL, NULL}
},
.flag = (struct SR_BIT[]) {
[ 0] = {DO_CPU , 1 , UNDEF_CR , 0 },
[ 1] = {DO_SPC , 1 , UNDEF_CR , 0 },
[ 2] = {DO_EL , 1 , EL0_64 , 1 },
[ 3] = {DO_EL , 1 , EL0_32 , 1 },
[ 4] = {DO_SPC , 1 , UNDEF_CR , 0 },
[ 5] = {DO_EL , 1 , EL1_64 , 1 },
[ 6] = {DO_EL , 1 , EL1_32 , 1 },
[ 7] = {DO_SPC , 1 , UNDEF_CR , 0 },
[ 8] = {DO_EL , 1 , EL2_64 , 1 },
[ 9] = {DO_EL , 1 , EL2_32 , 1 },
[10] = {DO_EL , 1 , EL2_SEC , 1 },
[11] = {DO_SPC , 1 , UNDEF_CR , 0 },
[12] = {DO_EL , 1 , EL3_64 , 1 },
[13] = {DO_EL , 1 , EL3_32 , 1 },
[14] = {DO_SPC , 1 , UNDEF_CR , 0 },
[15] = {DO_SPC , 1 , UNDEF_CR , 0 },
[16] = {DO_SPC , 1 , UNDEF_CR , 0 },
{DO_END , 1 , UNDEF_CR , 0 }
}
},
{
.header = (struct SR_HDR[]) {
[ 0] = {&RSC(SYS_REG_HDR_FPSR).CODE()[ 0],RSC(SYS_REG_FPSR).CODE()},
Expand Down Expand Up @@ -844,6 +904,11 @@ REASON_CODE SystemRegisters( Window *win,
PRT(REG, attrib[1], RSC(SYS_REGS_NA).CODE());
}
break;
case DO_EL:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.EL,
pFlag->pos, pFlag->len));
break;
case DO_FPSR:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.FPSR,
Expand Down
1 change: 1 addition & 0 deletions aarch64/corefreq.h
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Expand Up @@ -186,6 +186,7 @@ typedef struct
Bit64 FLAGS __attribute__ ((aligned (8)));
Bit64 SCTLR __attribute__ ((aligned (8)));
Bit64 SCTLR2 __attribute__ ((aligned (8)));
Bit64 EL __attribute__ ((aligned (8)));
Bit64 FPSR __attribute__ ((aligned (8)));
Bit64 SVCR __attribute__ ((aligned (8)));
} SystemRegister;
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3 changes: 3 additions & 0 deletions aarch64/corefreqd.c
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Expand Up @@ -824,6 +824,9 @@ void SystemRegisters( RO(SHM_STRUCT) *RO(Shm), RO(CORE) **RO(Core),
RO(Shm)->Cpu[cpu].SystemRegister.SCTLR2 = \
RO(Core, AT(cpu))->SystemRegister.SCTLR2;

RO(Shm)->Cpu[cpu].SystemRegister.EL = \
RO(Core, AT(cpu))->SystemRegister.EL;

RO(Shm)->Cpu[cpu].SystemRegister.FPSR = \
RO(Core, AT(cpu))->SystemRegister.FPSR;

Expand Down
42 changes: 38 additions & 4 deletions aarch64/corefreqk.c
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Expand Up @@ -1990,15 +1990,13 @@ static void Query_GenericMachine(unsigned int cpu)

void SystemRegisters(CORE_RO *Core)
{
volatile CPACR cpacr;
volatile AA64ISAR2 isar2;
volatile AA64MMFR1 mmfr1;
volatile AA64PFR0 pfr0;

isar2.value = MOV_SR_GPR(ID_AA64ISAR2_EL1);

__asm__ __volatile__(
"mrs %[cpacr], cpacr_el1" "\n\t"
"mrs %[sctlr], sctlr_el1" "\n\t"
"mrs %[mmfr1], id_aa64mmfr1_el1""\n\t"
"mrs %[pfr0] , id_aa64pfr0_el1""\n\t"
Expand All @@ -2013,8 +2011,7 @@ void SystemRegisters(CORE_RO *Core)
"orr %[flags], x14, x13" "\n\t"
"orr %[flags], %[flags], x12" "\n\t"
"orr %[flags], %[flags], x11"
: [cpacr] "=r" (cpacr),
[sctlr] "=r" (Core->SystemRegister.SCTLR),
: [sctlr] "=r" (Core->SystemRegister.SCTLR),
[mmfr1] "=r" (mmfr1),
[pfr0] "=r" (pfr0),
[fpsr] "=r" (Core->SystemRegister.FPSR),
Expand Down Expand Up @@ -2044,6 +2041,43 @@ void SystemRegisters(CORE_RO *Core)
} else {
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CLRBHB, Core->Bind);
}
switch (pfr0.EL3) {
case 0b0010:
BITSET(LOCKLESS, Core->SystemRegister.EL, EL3_32);
fallthrough;
case 0b0001:
BITSET(LOCKLESS, Core->SystemRegister.EL, EL3_64);
break;
}
switch (pfr0.EL2) {
case 0b0010:
BITSET(LOCKLESS, Core->SystemRegister.EL, EL2_32);
fallthrough;
case 0b0001:
BITSET(LOCKLESS, Core->SystemRegister.EL, EL2_64);
break;
}
switch (pfr0.SEL2) {
case 0b0001:
BITSET(LOCKLESS, Core->SystemRegister.EL, EL2_SEC);
break;
}
switch (pfr0.EL1) {
case 0b0010:
BITSET(LOCKLESS, Core->SystemRegister.EL, EL1_32);
fallthrough;
case 0b0001:
BITSET(LOCKLESS, Core->SystemRegister.EL, EL1_64);
break;
}
switch (pfr0.EL0) {
case 0b0010:
BITSET(LOCKLESS, Core->SystemRegister.EL, EL0_32);
fallthrough;
case 0b0001:
BITSET(LOCKLESS, Core->SystemRegister.EL, EL0_64);
break;
}
switch (pfr0.CSV2) {
case 0b0001:
BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
Expand Down
10 changes: 10 additions & 0 deletions aarch64/coretypes.h
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Expand Up @@ -210,6 +210,16 @@ enum SYS_REG {
SCTLR2_EnADERR = 3,
SCTLR2_NMEA = 2,

EL0_64 = 0,
EL0_32 = 1,
EL1_64 = 2,
EL1_32 = 3,
EL2_64 = 4,
EL2_32 = 5,
EL2_SEC = 6,
EL3_64 = 7,
EL3_32 = 8,

FPSR_N = 31,
FPSR_Z = 30,
FPSR_C = 29,
Expand Down

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