[AArch64] Add the number of AMU counters from AMCGCR register

cyring · Feb 9, 2024 · 637ff1a · 637ff1a
1 parent f2a12a5
commit 637ff1a
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Showing 2 changed files with 17 additions and 0 deletions.
diff --git a/aarch64/arm_reg.h b/aarch64/arm_reg.h
@@ -19,6 +19,7 @@
 #define MRS_ALLINT		sys_reg(0b11, 0b000, 0b0100, 0b0011, 0b000)
 #define MRS_PM			sys_reg(0b11, 0b000, 0b0100, 0b0011, 0b001)
 #define MRS_SVCR		sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b010)
+#define AMCGCR_EL0		sys_reg(0b11, 0b011, 0b1101, 0b0010, 0b010)
 #define CLUSTERCFR_EL1		sys_reg(0b11, 0b000, 0b1111, 0b0011, 0b000)
 
 typedef union
@@ -308,6 +309,18 @@ typedef union
 	};
 } CPACR;
 
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		CG0NC		:  8-0,
+		CG1NC		: 16-8,
+		RES0		: 64-16;
+	};
+} AMCGCR;
+
 typedef union
 {
 	unsigned long long	value;

diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c
@@ -1031,6 +1031,10 @@ static void Query_Features(void *pArg)
 		iArg->Features->AMU_frac = 0;
 		break;
 	}
+	if (iArg->Features->AMU_vers > 0) {
+		AMCGCR amcgc = {.value = MOV_SR_GPR(AMCGCR_EL0)};
+		iArg->Features->PerfMon.FixCtrs += amcgc.CG0NC + amcgc.CG1NC;
+	}
 	switch (pfr0.RME) {
 	case 0b0001:
 		iArg->Features->RME = 1;