update package

chiselverify · Dec 11, 2020 · 33b0000 · 33b0000
1 parent 40fe6e0
commit 33b0000
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Showing 4 changed files with 36 additions and 58 deletions.
diff --git a/axi4/src/main/scala/axi4/Interfaces.scala b/axi4/src/main/scala/axi4/Interfaces.scala
@@ -27,11 +27,11 @@ class MasterInterface(val addrW: Int, val dataW: Int, val idW: Int = 0, val user
    * [[ra]] is the read address channel
    * [[rd]] is the read data channel
    */
-  val wa = Decoupled(Output(WA(addrW, idW, userW))) //Decoupled(new WA(addrW, idW, userW))
-  val wd = Decoupled(Output(WD(dataW, userW))) //Decoupled(new WD(dataW, userW))
-  val wr = Flipped(Decoupled(Output(WR(idW, userW)))) //Flipped(Decoupled(Flipped(new WR(idW, userW))))
-  val ra = Decoupled(RA(addrW, idW, userW)) //Decoupled(new RA(addrW, idW, userW))
-  val rd = Flipped(Decoupled(Output(RD(dataW, idW, userW)))) //Flipped(Decoupled(Flipped(new RD(dataW, idW, userW))))
+  val wa = Decoupled(Output(WA(addrW, idW, userW)))
+  val wd = Decoupled(Output(WD(dataW, userW)))
+  val wr = Flipped(Decoupled(Output(WR(idW, userW))))
+  val ra = Decoupled(RA(addrW, idW, userW))
+  val rd = Flipped(Decoupled(Output(RD(dataW, idW, userW))))
 }
 
 /** AXI4 slave interface
@@ -50,9 +50,9 @@ class SlaveInterface(val addrW: Int, val dataW: Int, val idW: Int = 0, val userW
    * [[ra]] is the read address channel
    * [[rd]] is the read data channel
    */
-  val wa = Flipped(Decoupled(Output(WA(addrW, idW, userW)))) //Flipped(Decoupled(new WA(addrW, idW, userW)))
-  val wd = Flipped(Decoupled(Output(WD(dataW, userW)))) //Flipped(Decoupled(new WD(dataW, userW)))
-  val wr = Decoupled(Output(WR(idW, userW))) //Flipped(Flipped(Decoupled(Flipped(new WR(idW, userW)))))
-  val ra = Flipped(Decoupled(Output(RA(addrW, idW, userW)))) //Flipped(Decoupled(new RA(addrW, idW, userW)))
-  val rd = Decoupled(Output(RD(dataW, idW, userW))) //Flipped(Flipped(Decoupled(Flipped(new RD(dataW, idW, userW)))))
+  val wa = Flipped(Decoupled(Output(WA(addrW, idW, userW))))
+  val wd = Flipped(Decoupled(Output(WD(dataW, userW))))
+  val wr = Decoupled(Output(WR(idW, userW)))
+  val ra = Flipped(Decoupled(Output(RA(addrW, idW, userW))))
+  val rd = Decoupled(Output(RD(dataW, idW, userW)))
 }
diff --git a/axi4/src/main/scala/axi4/Master.scala b/axi4/src/main/scala/axi4/Master.scala
diff --git a/axi4/src/main/scala/axi4/Slave.scala b/axi4/src/main/scala/axi4/Slave.scala
diff --git a/axi4/src/main/scala/package.scala → axi4/src/main/scala/axi4/package.scala b/axi4/src/main/scala/package.scala → axi4/src/main/scala/axi4/package.scala
@@ -9,6 +9,32 @@
 import chisel3._
 
 package object axi4 {
+  /** AXI4 master
+   * 
+   * An empty class representing an AXI master
+   *
+   * @param addrW the width of the address signals in bits
+   * @param dataW the width of the data read/write signals in bits
+   * @param idW the width of the ID signals in bits, defaults to 0
+   * @param userW the width of the user signals in bits, defaults to 0
+   */
+  abstract class Master(val addrW: Int, val dataW: Int, val idW: Int = 0, val userW: Int = 0) extends Module {
+    val io = IO(new MasterInterface(addrW, dataW, idW, userW))
+  }
+
+  /** AXI4 slave
+   * 
+   * An empty class representing an AXI slave
+   *
+   * @param addrW the width of the address signals in bits
+   * @param dataW the width of the data read/write signals in bits
+   * @param idW the width of the ID signals in bits, defaults to 0
+   * @param userW the width of the user signals in bits, defaults to 0
+   */
+  abstract class Slave(val addrW: Int, val dataW: Int, val idW: Int = 0, val userW: Int = 0) extends Module {
+    val io = IO(new SlaveInterface(addrW, dataW, idW, userW))
+  }
+
   /** AXI4 burst encodings */
   object BurstEncodings {
     val Fixed             = "b00".U