chipsalliance · adkian-sifive · Oct 8, 2025 · Nov 19, 2025 · Nov 19, 2025 · Nov 19, 2025
diff --git a/src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala b/src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala
@@ -115,12 +115,12 @@ object OpaqueTypeSpec {
   class Boxed[T <: Data](gen: T) extends MaybeBoxed[T] {
     def boxed = true
     lazy val elements = SeqMap("underlying" -> gen)
-    def underlying = elements.head._2
+    def underlying = elements.head._2.asInstanceOf[T]
   }
   class Unboxed[T <: Data](gen: T) extends MaybeBoxed[T] with OpaqueType {
     def boxed = false
     lazy val elements = SeqMap("" -> gen)
-    def underlying = elements.head._2
+    def underlying = elements.head._2.asInstanceOf[T]
   }
 
   class MaybeNoAsUInt(noAsUInt: Boolean) extends Record with OpaqueType {

diff --git a/src/test/scala-2/chiselTests/interface/Drivers.scala b/src/test/scala-2/chiselTests/interface/Drivers.scala
@@ -5,7 +5,7 @@ import java.io.File
 import chisel3.RawModule
 import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage.{ChiselStage, FirtoolOption}
-import firrtl.AnnotationSeq
+import firrtl.{seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{StageError, StageUtils}
 import sys.process._
 

diff --git a/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala b/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala
@@ -7,7 +7,7 @@ import chisel3.simulator._
 import chisel3.util.{HasExtModuleInline, HasExtModulePath, HasExtModuleResource}
 import org.scalatest.funspec.AnyFunSpec
 import org.scalatest.matchers.must.Matchers
-import org.scalatest.matchers.should.Matchers.convertToAnyShouldWrapper
+// import org.scalatest.matchers.should.Matchers.convertToStringShouldWrapperForVerb
 import svsim._
 
 class VerilatorSimulator(val workspacePath: String) extends Simulator[verilator.Backend] {

diff --git a/...-2/circtTests/stage/ChiselStageSpec.scala → ...2/chiselTests/stage/ChiselStageSpec.scala b/...-2/circtTests/stage/ChiselStageSpec.scala → ...2/chiselTests/stage/ChiselStageSpec.scala
@@ -123,12 +123,12 @@ object ChiselStageSpec {
   }
 
   class RecoverableErrorFakeSourceInfo extends RawModule {
-    implicit val info = SourceLine("Foo", 3, 10)
+    implicit val info: SourceLine = SourceLine("Foo", 3, 10)
     3.U >> -1
   }
 
   class ErrorCaughtByFirtool extends RawModule {
-    implicit val info = SourceLine("Foo", 3, 10)
+    implicit val info: SourceLine = SourceLine("Foo", 3, 10)
     val w = Wire(UInt(8.W))
   }
 

diff --git a/...est/scala-2/chisel3/PlaceholderSpec.scala → src/test/scala/chisel3/PlaceholderSpec.scala b/...est/scala-2/chisel3/PlaceholderSpec.scala → src/test/scala/chisel3/PlaceholderSpec.scala
diff --git a/.../chisel3/internal/ContainsProbeSpec.scala → .../chisel3/internal/ContainsProbeSpec.scala b/.../chisel3/internal/ContainsProbeSpec.scala → .../chisel3/internal/ContainsProbeSpec.scala
diff --git a/.../chisel3/internal/NameCollisionSpec.scala → .../chisel3/internal/NameCollisionSpec.scala b/.../chisel3/internal/NameCollisionSpec.scala → .../chisel3/internal/NameCollisionSpec.scala
diff --git a/...la-2/chisel3/internal/NamespaceSpec.scala → ...cala/chisel3/internal/NamespaceSpec.scala b/...la-2/chisel3/internal/NamespaceSpec.scala → ...cala/chisel3/internal/NamespaceSpec.scala
diff --git a/...chisel3/stage/ChiselOptionsViewSpec.scala → ...chisel3/stage/ChiselOptionsViewSpec.scala b/...chisel3/stage/ChiselOptionsViewSpec.scala → ...chisel3/stage/ChiselOptionsViewSpec.scala
@@ -3,7 +3,7 @@
 package chisel3.stage
 
 import firrtl.options.Viewer.view
-import firrtl.RenameMap
+import firrtl.{seqToAnnoSeq, RenameMap}
 
 import chisel3.ElaboratedCircuit
 import chisel3.stage._

diff --git a/...t/scala-2/chisel3/testers/TestUtils.scala → ...est/scala/chisel3/testers/TestUtils.scala b/...t/scala-2/chisel3/testers/TestUtils.scala → ...est/scala/chisel3/testers/TestUtils.scala
diff --git a/.../experimental/decode/TruthTableSpec.scala → .../experimental/decode/TruthTableSpec.scala b/.../experimental/decode/TruthTableSpec.scala → .../experimental/decode/TruthTableSpec.scala
diff --git a/src/test/scala-2/chiselTests/AdderTree.scala → src/test/scala/chiselTests/AdderTree.scala b/src/test/scala-2/chiselTests/AdderTree.scala → src/test/scala/chiselTests/AdderTree.scala
@@ -20,7 +20,7 @@ class AdderTreeTester(bitWidth: Int, numsToAdd: List[Int]) extends Module {
   val dut = Module(new AdderTree(genType, numsToAdd.size))
   dut.io.numIn := VecInit(numsToAdd.map(x => x.asUInt(bitWidth.W)))
   val sumCorrect = dut.io.numOut === (numsToAdd.reduce(_ + _) % (1 << bitWidth)).asUInt(bitWidth.W)
-  assert(sumCorrect)
+  chisel3.assert(sumCorrect)
   stop()
 }
 

diff --git a/...2/chiselTests/AnalogIntegrationSpec.scala → ...a/chiselTests/AnalogIntegrationSpec.scala b/...2/chiselTests/AnalogIntegrationSpec.scala → ...a/chiselTests/AnalogIntegrationSpec.scala
diff --git a/...test/scala-2/chiselTests/AnalogSpec.scala → src/test/scala/chiselTests/AnalogSpec.scala b/...test/scala-2/chiselTests/AnalogSpec.scala → src/test/scala/chiselTests/AnalogSpec.scala
diff --git a/...2/chiselTests/AnnotatingDiamondSpec.scala → ...a/chiselTests/AnnotatingDiamondSpec.scala b/...2/chiselTests/AnnotatingDiamondSpec.scala → ...a/chiselTests/AnnotatingDiamondSpec.scala
diff --git a/...-2/chiselTests/AnnotationInlineSpec.scala → ...la/chiselTests/AnnotationInlineSpec.scala b/...-2/chiselTests/AnnotationInlineSpec.scala → ...la/chiselTests/AnnotationInlineSpec.scala
diff --git a/...ala-2/chiselTests/AnnotationNoDedup.scala → ...scala/chiselTests/AnnotationNoDedup.scala b/...ala-2/chiselTests/AnnotationNoDedup.scala → ...scala/chiselTests/AnnotationNoDedup.scala
diff --git a/src/test/scala-2/chiselTests/Assert.scala → src/test/scala/chiselTests/Assert.scala b/src/test/scala-2/chiselTests/Assert.scala → src/test/scala/chiselTests/Assert.scala
diff --git a/.../scala-2/chiselTests/AsyncResetSpec.scala → ...st/scala/chiselTests/AsyncResetSpec.scala b/.../scala-2/chiselTests/AsyncResetSpec.scala → ...st/scala/chiselTests/AsyncResetSpec.scala
diff --git a/...ala-2/chiselTests/AutoClonetypeSpec.scala → ...scala/chiselTests/AutoClonetypeSpec.scala b/...ala-2/chiselTests/AutoClonetypeSpec.scala → ...scala/chiselTests/AutoClonetypeSpec.scala
@@ -344,7 +344,7 @@ class AutoClonetypeSpec extends AnyFlatSpec with Matchers {
     }
     emitCHIRRTL {
       new Module {
-        implicit val x = 8
+        implicit val x: Int = 8
         val in = IO(Input(new MyBundle))
         val out = IO(Output(new MyBundle))
         out := in

diff --git a/...ala-2/chiselTests/BetterNamingTests.scala → ...scala/chiselTests/BetterNamingTests.scala b/...ala-2/chiselTests/BetterNamingTests.scala → ...scala/chiselTests/BetterNamingTests.scala
diff --git a/...test/scala-2/chiselTests/BitwiseOps.scala → src/test/scala/chiselTests/BitwiseOps.scala b/...test/scala-2/chiselTests/BitwiseOps.scala → src/test/scala/chiselTests/BitwiseOps.scala
diff --git a/src/test/scala-2/chiselTests/BlackBox.scala → src/test/scala/chiselTests/BlackBox.scala b/src/test/scala-2/chiselTests/BlackBox.scala → src/test/scala/chiselTests/BlackBox.scala
@@ -361,7 +361,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     object A extends layer.Layer(layer.LayerConfig.Extract())
 
     sealed trait NoIo { this: BlackBox =>
-      final val io = IO(new Bundle {})
+      final val io = chisel3.IO(new Bundle {})
     }
 
     // No known layers
@@ -401,7 +401,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     class Bar extends BlackBox {
       final val io = IO {
         new Bundle {
-          val a = Output(probe.Probe(Bool(), layers.Verification))
+          val a = Output(probe.Probe(Bool(), chisel3.layers.Verification))
         }
       }
     }
@@ -411,7 +411,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     class Baz extends BlackBox(knownLayers = Seq(A)) {
       final val io = IO {
         new Bundle {
-          val a = Output(probe.Probe(Bool(), layers.Verification))
+          val a = Output(probe.Probe(Bool(), chisel3.layers.Verification))
         }
       }
     }

diff --git a/...st/scala-2/chiselTests/BlackBoxImpl.scala → ...test/scala/chiselTests/BlackBoxImpl.scala b/...st/scala-2/chiselTests/BlackBoxImpl.scala → ...test/scala/chiselTests/BlackBoxImpl.scala
diff --git a/src/test/scala-2/chiselTests/BoolSpec.scala → src/test/scala/chiselTests/BoolSpec.scala b/src/test/scala-2/chiselTests/BoolSpec.scala → src/test/scala/chiselTests/BoolSpec.scala
diff --git a/...scala-2/chiselTests/BulkConnectSpec.scala → ...t/scala/chiselTests/BulkConnectSpec.scala b/...scala-2/chiselTests/BulkConnectSpec.scala → ...t/scala/chiselTests/BulkConnectSpec.scala
@@ -73,7 +73,7 @@ class BulkConnectSpec extends AnyPropSpec with Matchers {
     val chirrtl = ChiselStage.emitCHIRRTL(new Module {
       val io: MyBundle = IO(Flipped(new MyBundle))
 
-      val bb = Module(new BlackBox {
+      val bb = Module[BlackBox { def io: MyBundle }](new BlackBox {
         val io: MyBundle = IO(Flipped(new MyBundle))
       })
 

diff --git a/...test/scala-2/chiselTests/BundleWire.scala → src/test/scala/chiselTests/BundleWire.scala b/...test/scala-2/chiselTests/BundleWire.scala → src/test/scala/chiselTests/BundleWire.scala
diff --git a/...chiselTests/ChiselTestUtilitiesSpec.scala → ...chiselTests/ChiselTestUtilitiesSpec.scala b/...chiselTests/ChiselTestUtilitiesSpec.scala → ...chiselTests/ChiselTestUtilitiesSpec.scala
diff --git a/src/test/scala-2/chiselTests/ClockSpec.scala → src/test/scala/chiselTests/ClockSpec.scala b/src/test/scala-2/chiselTests/ClockSpec.scala → src/test/scala/chiselTests/ClockSpec.scala
diff --git a/...est/scala-2/chiselTests/ConnectSpec.scala → src/test/scala/chiselTests/ConnectSpec.scala b/...est/scala-2/chiselTests/ConnectSpec.scala → src/test/scala/chiselTests/ConnectSpec.scala
diff --git a/src/test/scala-2/chiselTests/ConstSpec.scala → src/test/scala/chiselTests/ConstSpec.scala b/src/test/scala-2/chiselTests/ConstSpec.scala → src/test/scala/chiselTests/ConstSpec.scala
diff --git a/src/test/scala-2/chiselTests/Counter.scala → src/test/scala/chiselTests/Counter.scala b/src/test/scala-2/chiselTests/Counter.scala → src/test/scala/chiselTests/Counter.scala
diff --git a/...st/scala-2/chiselTests/CustomBundle.scala → ...test/scala/chiselTests/CustomBundle.scala b/...st/scala-2/chiselTests/CustomBundle.scala → ...test/scala/chiselTests/CustomBundle.scala
diff --git a/src/test/scala-2/chiselTests/Decoder.scala → src/test/scala/chiselTests/Decoder.scala b/src/test/scala-2/chiselTests/Decoder.scala → src/test/scala/chiselTests/Decoder.scala
@@ -14,7 +14,7 @@ class Decoder(bitpats: List[String]) extends Module {
     val inst = Input(UInt(32.W))
     val matched = Output(Bool())
   })
-  io.matched := VecInit(bitpats.map(BitPat(_) === io.inst)).reduce(_ || _)
+  io.matched := VecInit(bitpats.map(BitPat(_) === io.inst).reduce(_ || _))
 }
 
 class DecoderTester(pairs: List[(String, String)]) extends Module {

diff --git a/...t/scala-2/chiselTests/DecoupledSpec.scala → ...est/scala/chiselTests/DecoupledSpec.scala b/...t/scala-2/chiselTests/DecoupledSpec.scala → ...est/scala/chiselTests/DecoupledSpec.scala
diff --git a/src/test/scala-2/chiselTests/DedupSpec.scala → src/test/scala/chiselTests/DedupSpec.scala b/src/test/scala-2/chiselTests/DedupSpec.scala → src/test/scala/chiselTests/DedupSpec.scala
diff --git a/...est/scala-2/chiselTests/DisableSpec.scala → src/test/scala/chiselTests/DisableSpec.scala b/...est/scala-2/chiselTests/DisableSpec.scala → src/test/scala/chiselTests/DisableSpec.scala
diff --git a/...t/scala-2/chiselTests/DontTouchSpec.scala → ...est/scala/chiselTests/DontTouchSpec.scala b/...t/scala-2/chiselTests/DontTouchSpec.scala → ...est/scala/chiselTests/DontTouchSpec.scala
diff --git a/...a-2/chiselTests/EnableShiftRegister.scala → ...ala/chiselTests/EnableShiftRegister.scala b/...a-2/chiselTests/EnableShiftRegister.scala → ...ala/chiselTests/EnableShiftRegister.scala
diff --git a/src/test/scala-2/chiselTests/EnumSpec.scala → src/test/scala/chiselTests/EnumSpec.scala b/src/test/scala-2/chiselTests/EnumSpec.scala → src/test/scala/chiselTests/EnumSpec.scala
diff --git a/src/test/scala-2/chiselTests/ExtModule.scala → src/test/scala/chiselTests/ExtModule.scala b/src/test/scala-2/chiselTests/ExtModule.scala → src/test/scala/chiselTests/ExtModule.scala
diff --git a/...t/scala-2/chiselTests/ExtModuleImpl.scala → ...est/scala/chiselTests/ExtModuleImpl.scala b/...t/scala-2/chiselTests/ExtModuleImpl.scala → ...est/scala/chiselTests/ExtModuleImpl.scala
diff --git a/src/test/scala-2/chiselTests/GCD.scala → src/test/scala/chiselTests/GCD.scala b/src/test/scala-2/chiselTests/GCD.scala → src/test/scala/chiselTests/GCD.scala
diff --git a/...scala-2/chiselTests/IOCompatibility.scala → ...t/scala/chiselTests/IOCompatibility.scala b/...scala-2/chiselTests/IOCompatibility.scala → ...t/scala/chiselTests/IOCompatibility.scala
diff --git a/.../scala-2/chiselTests/IllegalRefSpec.scala → ...st/scala/chiselTests/IllegalRefSpec.scala b/.../scala-2/chiselTests/IllegalRefSpec.scala → ...st/scala/chiselTests/IllegalRefSpec.scala
diff --git a/...chiselTests/ImplicitConversionsSpec.scala → ...chiselTests/ImplicitConversionsSpec.scala b/...chiselTests/ImplicitConversionsSpec.scala → ...chiselTests/ImplicitConversionsSpec.scala
diff --git a/...test/scala-2/chiselTests/InlineSpec.scala → src/test/scala/chiselTests/InlineSpec.scala b/...test/scala-2/chiselTests/InlineSpec.scala → src/test/scala/chiselTests/InlineSpec.scala
diff --git a/...scala-2/chiselTests/IntegerMathSpec.scala → ...t/scala/chiselTests/IntegerMathSpec.scala b/...scala-2/chiselTests/IntegerMathSpec.scala → ...t/scala/chiselTests/IntegerMathSpec.scala
diff --git a/...scala-2/chiselTests/IntrinsicModule.scala → ...t/scala/chiselTests/IntrinsicModule.scala b/...scala-2/chiselTests/IntrinsicModule.scala → ...t/scala/chiselTests/IntrinsicModule.scala
diff --git a/...t/scala-2/chiselTests/IntrinsicSpec.scala → ...est/scala/chiselTests/IntrinsicSpec.scala b/...t/scala-2/chiselTests/IntrinsicSpec.scala → ...est/scala/chiselTests/IntrinsicSpec.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import chisel3._
 import circt.stage.ChiselStage
+import chisel3.experimental.{fromIntToIntParam, fromStringToStringParam}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 

diff --git a/...ala-2/chiselTests/InvalidateAPISpec.scala → ...scala/chiselTests/InvalidateAPISpec.scala b/...ala-2/chiselTests/InvalidateAPISpec.scala → ...scala/chiselTests/InvalidateAPISpec.scala
diff --git a/...t/scala-2/chiselTests/LazyCloneSpec.scala → ...est/scala/chiselTests/LazyCloneSpec.scala b/...t/scala-2/chiselTests/LazyCloneSpec.scala → ...est/scala/chiselTests/LazyCloneSpec.scala
diff --git a/...-2/chiselTests/LiteralExtractorSpec.scala → ...la/chiselTests/LiteralExtractorSpec.scala b/...-2/chiselTests/LiteralExtractorSpec.scala → ...la/chiselTests/LiteralExtractorSpec.scala
diff --git a/...a-2/chiselTests/LiteralToTargetSpec.scala → ...ala/chiselTests/LiteralToTargetSpec.scala b/...a-2/chiselTests/LiteralToTargetSpec.scala → ...ala/chiselTests/LiteralToTargetSpec.scala
@@ -8,11 +8,8 @@ import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
 
 class LiteralToTargetSpec extends AnyFreeSpec with Matchers {
-
   "Literal Data should fail to be converted to ReferenceTarget" in {
-
-    (the[ChiselException] thrownBy {
-
+    val ex = the[ChiselException] thrownBy {
       class Bar extends RawModule {
         val a = 1.U
       }
@@ -23,6 +20,8 @@ class LiteralToTargetSpec extends AnyFreeSpec with Matchers {
       }
 
       ChiselStage.emitCHIRRTL(new Foo)
-    } should have).message("Illegal component name: UInt<1>(0h1) (note: literals are illegal)")
+    }
+
+    ex.getMessage shouldBe "Illegal component name: UInt<1>(0h1) (note: literals are illegal)"
   }
 }
diff --git a/.../chiselTests/LoadMemoryFromFileSpec.scala → .../chiselTests/LoadMemoryFromFileSpec.scala b/.../chiselTests/LoadMemoryFromFileSpec.scala → .../chiselTests/LoadMemoryFromFileSpec.scala
diff --git a/src/test/scala-2/chiselTests/LogUtils.scala → src/test/scala/chiselTests/LogUtils.scala b/src/test/scala-2/chiselTests/LogUtils.scala → src/test/scala/chiselTests/LogUtils.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import java.io.{ByteArrayOutputStream, PrintStream}
 import logger.{LogLevel, LogLevelAnnotation, Logger}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 
 trait LogUtils {
 

diff --git a/src/test/scala-2/chiselTests/Math.scala → src/test/scala/chiselTests/Math.scala b/src/test/scala-2/chiselTests/Math.scala → src/test/scala/chiselTests/Math.scala
diff --git a/...st/scala-2/chiselTests/MemorySearch.scala → ...test/scala/chiselTests/MemorySearch.scala b/...st/scala-2/chiselTests/MemorySearch.scala → ...test/scala/chiselTests/MemorySearch.scala
diff --git a/...st/scala-2/chiselTests/MixedVecSpec.scala → ...test/scala/chiselTests/MixedVecSpec.scala b/...st/scala-2/chiselTests/MixedVecSpec.scala → ...test/scala/chiselTests/MixedVecSpec.scala
diff --git a/...cala-2/chiselTests/ModuleChoiceSpec.scala → .../scala/chiselTests/ModuleChoiceSpec.scala b/...cala-2/chiselTests/ModuleChoiceSpec.scala → .../scala/chiselTests/ModuleChoiceSpec.scala
@@ -34,8 +34,8 @@ class ModuleWithChoice[T <: Data](
   default: => FixedIOBaseModule[T]
 )(alternateImpls: Seq[(Case, () => FixedIOBaseModule[T])])
     extends Module {
-  val inst = ModuleChoice(default)(alternateImpls)
-  val io = IO(inst.cloneType)
+  val inst: T = ModuleChoice[T](default, alternateImpls)
+  val io:   T = IO(chiselTypeOf(inst))
   io <> inst
 }
 

diff --git a/...test/scala-2/chiselTests/ModuleSpec.scala → src/test/scala/chiselTests/ModuleSpec.scala b/...test/scala-2/chiselTests/ModuleSpec.scala → src/test/scala/chiselTests/ModuleSpec.scala
@@ -9,6 +9,7 @@ import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage.{CIRCTTarget, CIRCTTargetAnnotation, ChiselStage, FirtoolOption}
 import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.{TargetDirAnnotation, Unserializable}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import org.scalatest.matchers.should.Matchers
 import org.scalatest.propspec.AnyPropSpec
 import scala.io.Source

diff --git a/src/test/scala-2/chiselTests/MulLookup.scala → src/test/scala/chiselTests/MulLookup.scala b/src/test/scala-2/chiselTests/MulLookup.scala → src/test/scala/chiselTests/MulLookup.scala
diff --git a/...est/scala-2/chiselTests/MultiAssign.scala → src/test/scala/chiselTests/MultiAssign.scala b/...est/scala-2/chiselTests/MultiAssign.scala → src/test/scala/chiselTests/MultiAssign.scala
diff --git a/.../scala-2/chiselTests/MultiClockSpec.scala → ...st/scala/chiselTests/MultiClockSpec.scala b/.../scala-2/chiselTests/MultiClockSpec.scala → ...st/scala/chiselTests/MultiClockSpec.scala
diff --git a/...ala-2/chiselTests/NamedModuleTester.scala → ...scala/chiselTests/NamedModuleTester.scala b/...ala-2/chiselTests/NamedModuleTester.scala → ...scala/chiselTests/NamedModuleTester.scala
diff --git a/...t/scala-2/chiselTests/OneHotMuxSpec.scala → ...est/scala/chiselTests/OneHotMuxSpec.scala b/...t/scala-2/chiselTests/OneHotMuxSpec.scala → ...est/scala/chiselTests/OneHotMuxSpec.scala
diff --git a/...st/scala-2/chiselTests/OptionBundle.scala → ...test/scala/chiselTests/OptionBundle.scala b/...st/scala-2/chiselTests/OptionBundle.scala → ...test/scala/chiselTests/OptionBundle.scala
diff --git a/src/test/scala-2/chiselTests/Padding.scala → src/test/scala/chiselTests/Padding.scala b/src/test/scala-2/chiselTests/Padding.scala → src/test/scala/chiselTests/Padding.scala
diff --git a/...a-2/chiselTests/ParameterizedModule.scala → ...ala/chiselTests/ParameterizedModule.scala b/...a-2/chiselTests/ParameterizedModule.scala → ...ala/chiselTests/ParameterizedModule.scala
diff --git a/src/test/scala-2/chiselTests/PopCount.scala → src/test/scala/chiselTests/PopCount.scala b/src/test/scala-2/chiselTests/PopCount.scala → src/test/scala/chiselTests/PopCount.scala
diff --git a/src/test/scala-2/chiselTests/PortSpec.scala → src/test/scala/chiselTests/PortSpec.scala b/src/test/scala-2/chiselTests/PortSpec.scala → src/test/scala/chiselTests/PortSpec.scala
diff --git a/...t/scala-2/chiselTests/PrintableSpec.scala → ...est/scala/chiselTests/PrintableSpec.scala b/...t/scala-2/chiselTests/PrintableSpec.scala → ...est/scala/chiselTests/PrintableSpec.scala
diff --git a/src/test/scala-2/chiselTests/Printf.scala → src/test/scala/chiselTests/Printf.scala b/src/test/scala-2/chiselTests/Printf.scala → src/test/scala/chiselTests/Printf.scala
diff --git a/...t/scala-2/chiselTests/PropertyUtils.scala → ...est/scala/chiselTests/PropertyUtils.scala b/...t/scala-2/chiselTests/PropertyUtils.scala → ...est/scala/chiselTests/PropertyUtils.scala
diff --git a/...st/scala-2/chiselTests/ReadOnlySpec.scala → ...test/scala/chiselTests/ReadOnlySpec.scala b/...st/scala-2/chiselTests/ReadOnlySpec.scala → ...test/scala/chiselTests/ReadOnlySpec.scala
diff --git a/...t/scala-2/chiselTests/RebindingSpec.scala → ...est/scala/chiselTests/RebindingSpec.scala b/...t/scala-2/chiselTests/RebindingSpec.scala → ...est/scala/chiselTests/RebindingSpec.scala
diff --git a/...test/scala-2/chiselTests/RecordSpec.scala → src/test/scala/chiselTests/RecordSpec.scala b/...test/scala-2/chiselTests/RecordSpec.scala → src/test/scala/chiselTests/RecordSpec.scala
diff --git a/.../scala-2/chiselTests/ReduceTreeSpec.scala → ...st/scala/chiselTests/ReduceTreeSpec.scala b/.../scala-2/chiselTests/ReduceTreeSpec.scala → ...st/scala/chiselTests/ReduceTreeSpec.scala
diff --git a/src/test/scala-2/chiselTests/RegSpec.scala → src/test/scala/chiselTests/RegSpec.scala b/src/test/scala-2/chiselTests/RegSpec.scala → src/test/scala/chiselTests/RegSpec.scala
diff --git a/src/test/scala-2/chiselTests/ResetSpec.scala → src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala-2/chiselTests/ResetSpec.scala → src/test/scala/chiselTests/ResetSpec.scala
diff --git a/src/test/scala-2/chiselTests/Risc.scala → src/test/scala/chiselTests/Risc.scala b/src/test/scala-2/chiselTests/Risc.scala → src/test/scala/chiselTests/Risc.scala
diff --git a/src/test/scala-2/chiselTests/SIntOps.scala → src/test/scala/chiselTests/SIntOps.scala b/src/test/scala-2/chiselTests/SIntOps.scala → src/test/scala/chiselTests/SIntOps.scala
@@ -202,13 +202,13 @@ class SIntOpsSpec extends AnyPropSpec with Matchers with ShiftRightWidthBehavior
   }
 
   property("Static right-shift should have a minimum width of 1") {
-    testShiftRightWidthBehavior(SInt)(chiselMinWidth = 1, firrtlMinWidth = 1)
+    testSIntShiftRightWidthBehavior(chiselMinWidth = 1, firrtlMinWidth = 1)
   }
 
   property("Static right-shift should have width of 0 in Chisel and 1 in FIRRTL with --use-legacy-width") {
     val args = Array("--use-legacy-width")
 
-    testShiftRightWidthBehavior(SInt)(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
+    testSIntShiftRightWidthBehavior(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
 
     // Focused test to show the mismatch
     class TestModule extends Module {

diff --git a/...test/scala-2/chiselTests/SimLogSpec.scala → src/test/scala/chiselTests/SimLogSpec.scala b/...test/scala-2/chiselTests/SimLogSpec.scala → src/test/scala/chiselTests/SimLogSpec.scala
@@ -33,7 +33,7 @@ class SimLogSpec extends AnyFlatSpec with Matchers with FileCheck with ChiselSim
     class MyModule extends Module {
       val in = IO(Input(UInt(8.W)))
       val fd = SimLog.file("logfile.log")
-      fd.printf("in = %d\n", in)
+      // fd.printf("in = %d\n", in)
     }
     ChiselStage
       .emitCHIRRTL(new MyModule)

diff --git a/...ala-2/chiselTests/SourceLocatorSpec.scala → ...scala/chiselTests/SourceLocatorSpec.scala b/...ala-2/chiselTests/SourceLocatorSpec.scala → ...scala/chiselTests/SourceLocatorSpec.scala
diff --git a/src/test/scala-2/chiselTests/Stack.scala → src/test/scala/chiselTests/Stack.scala b/src/test/scala-2/chiselTests/Stack.scala → src/test/scala/chiselTests/Stack.scala
diff --git a/src/test/scala-2/chiselTests/Stop.scala → src/test/scala/chiselTests/Stop.scala b/src/test/scala-2/chiselTests/Stop.scala → src/test/scala/chiselTests/Stop.scala
diff --git a/...test/scala-2/chiselTests/SwitchSpec.scala → src/test/scala/chiselTests/SwitchSpec.scala b/...test/scala-2/chiselTests/SwitchSpec.scala → src/test/scala/chiselTests/SwitchSpec.scala
diff --git a/src/test/scala-2/chiselTests/Tbl.scala → src/test/scala/chiselTests/Tbl.scala b/src/test/scala-2/chiselTests/Tbl.scala → src/test/scala/chiselTests/Tbl.scala
diff --git a/...t/scala-2/chiselTests/TypeAliasSpec.scala → ...est/scala/chiselTests/TypeAliasSpec.scala b/...t/scala-2/chiselTests/TypeAliasSpec.scala → ...est/scala/chiselTests/TypeAliasSpec.scala
diff --git a/src/test/scala-2/chiselTests/UIntOps.scala → src/test/scala/chiselTests/UIntOps.scala b/src/test/scala-2/chiselTests/UIntOps.scala → src/test/scala/chiselTests/UIntOps.scala
@@ -214,62 +214,100 @@ class UIntLitZeroWidthTester extends Module {
 }
 
 trait ShiftRightWidthBehavior extends WidthHelpers {
-  // The UInt and SInt objects don't share a type, so make one up that they can conform to structurally
-  type BitsFactory[T <: Bits] = {
-    def apply():         T
-    def apply(w: Width): T
+  def testSIntShiftRightWidthBehavior(chiselMinWidth: Int, firrtlMinWidth: Int, args: Iterable[String] = Nil): Unit = {
+    assertKnownWidth(4, args) {
+      val in = IO(Input(SInt(8.W)))
+      in >> 4
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      in >> 8
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      in >> 16
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      in >> 8
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      in >> 0
+    }
+    assertInferredWidth(4, args) {
+      val in = IO(Input(SInt(8.W)))
+      val w = WireInit(SInt(), in)
+      w >> 4
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      val w = WireInit(SInt(), in)
+      w >> 8
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      val w = WireInit(SInt(), in)
+      w >> 16
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      val w = WireInit(SInt(), in)
+      w >> 8
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      val w = WireInit(SInt(), in)
+      w >> 0
+    }
   }
-
-  def testShiftRightWidthBehavior[T <: Bits](
-    factory: BitsFactory[T]
-  )(chiselMinWidth: Int, firrtlMinWidth: Int, args: Iterable[String] = Nil): Unit = {
+  def testUIntShiftRightWidthBehavior(chiselMinWidth: Int, firrtlMinWidth: Int, args: Iterable[String] = Nil): Unit = {
     assertKnownWidth(4, args) {
-      val in = IO(Input(factory(8.W)))
+      val in = IO(Input(UInt(8.W)))
       in >> 4
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
+      val in = IO(Input(UInt(8.W)))
       in >> 8
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
+      val in = IO(Input(UInt(8.W)))
       in >> 16
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
+      val in = IO(Input(UInt(0.W)))
       in >> 8
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
+      val in = IO(Input(UInt(0.W)))
       in >> 0
     }
     assertInferredWidth(4, args) {
-      val in = IO(Input(factory(8.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(8.W)))
+      val w = WireInit(UInt(), in)
       w >> 4
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(8.W)))
+      val w = WireInit(UInt(), in)
       w >> 8
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(8.W)))
+      val w = WireInit(UInt(), in)
       w >> 16
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(0.W)))
+      val w = WireInit(UInt(), in)
       w >> 8
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(0.W)))
+      val w = WireInit(UInt(), in)
       w >> 0
     }
   }
-
 }
 
 class UIntOpsSpec extends AnyPropSpec with Matchers with LogUtils with ShiftRightWidthBehavior with ChiselSim {
@@ -551,13 +589,13 @@ class UIntOpsSpec extends AnyPropSpec with Matchers with LogUtils with ShiftRigh
   }
 
   property("Static right-shift should have a minimum width of 0") {
-    testShiftRightWidthBehavior(UInt)(chiselMinWidth = 0, firrtlMinWidth = 0)
+    testUIntShiftRightWidthBehavior(chiselMinWidth = 0, firrtlMinWidth = 0)
   }
 
   property("Static right-shift should have width of 0 in Chisel and 1 in FIRRTL with --use-legacy-width") {
     val args = Array("--use-legacy-width")
 
-    testShiftRightWidthBehavior(UInt)(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
+    testUIntShiftRightWidthBehavior(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
 
     // Focused test to show the mismatch
     class TestModule extends Module {

diff --git a/...cala-2/chiselTests/UnitTestMainSpec.scala → .../scala/chiselTests/UnitTestMainSpec.scala b/...cala-2/chiselTests/UnitTestMainSpec.scala → .../scala/chiselTests/UnitTestMainSpec.scala
diff --git a/src/test/scala-2/chiselTests/Util.scala → src/test/scala/chiselTests/Util.scala b/src/test/scala-2/chiselTests/Util.scala → src/test/scala/chiselTests/Util.scala
diff --git a/src/test/scala-2/chiselTests/ValidSpec.scala → src/test/scala/chiselTests/ValidSpec.scala b/src/test/scala-2/chiselTests/ValidSpec.scala → src/test/scala/chiselTests/ValidSpec.scala
diff --git a/src/test/scala-2/chiselTests/Vec.scala → src/test/scala/chiselTests/Vec.scala b/src/test/scala-2/chiselTests/Vec.scala → src/test/scala/chiselTests/Vec.scala
diff --git a/...scala-2/chiselTests/VecToTargetSpec.scala → ...t/scala/chiselTests/VecToTargetSpec.scala b/...scala-2/chiselTests/VecToTargetSpec.scala → ...t/scala/chiselTests/VecToTargetSpec.scala
diff --git a/.../scala-2/chiselTests/VectorPacketIO.scala → ...st/scala/chiselTests/VectorPacketIO.scala b/.../scala-2/chiselTests/VectorPacketIO.scala → ...st/scala/chiselTests/VectorPacketIO.scala
diff --git a/...cala-2/chiselTests/VerificationSpec.scala → .../scala/chiselTests/VerificationSpec.scala b/...cala-2/chiselTests/VerificationSpec.scala → .../scala/chiselTests/VerificationSpec.scala
diff --git a/src/test/scala-2/chiselTests/WhenSpec.scala → src/test/scala/chiselTests/WhenSpec.scala b/src/test/scala-2/chiselTests/WhenSpec.scala → src/test/scala/chiselTests/WhenSpec.scala
diff --git a/src/test/scala-2/chiselTests/WidthSpec.scala → src/test/scala/chiselTests/WidthSpec.scala b/src/test/scala-2/chiselTests/WidthSpec.scala → src/test/scala/chiselTests/WidthSpec.scala
diff --git a/src/test/scala-2/chiselTests/WireSpec.scala → src/test/scala/chiselTests/WireSpec.scala b/src/test/scala-2/chiselTests/WireSpec.scala → src/test/scala/chiselTests/WireSpec.scala
diff --git a/...Tests/naming/IdentifierProposerSpec.scala → ...Tests/naming/IdentifierProposerSpec.scala b/...Tests/naming/IdentifierProposerSpec.scala → ...Tests/naming/IdentifierProposerSpec.scala
diff --git a/...2/chiselTests/naming/NamePluginSpec.scala → ...a/chiselTests/naming/NamePluginSpec.scala b/...2/chiselTests/naming/NamePluginSpec.scala → ...a/chiselTests/naming/NamePluginSpec.scala
@@ -3,7 +3,6 @@
 package chiselTests.naming
 
 import chisel3._
-import chisel3.aop.Select
 import chisel3.experimental.prefix
 import chisel3.experimental.AffectsChiselName
 import chisel3.testing.scalatest.FileCheck

diff --git a/...ala-2/chiselTests/naming/PrefixSpec.scala → ...scala/chiselTests/naming/PrefixSpec.scala b/...ala-2/chiselTests/naming/PrefixSpec.scala → ...scala/chiselTests/naming/PrefixSpec.scala
@@ -3,7 +3,6 @@
 package chiselTests.naming
 
 import chisel3._
-import chisel3.aop.Select
 import chisel3.experimental.{noPrefix, prefix, skipPrefix, AffectsChiselPrefix}
 import chisel3.testing.scalatest.FileCheck
 import circt.stage.ChiselStage

diff --git a/...a-2/chiselTests/naming/TypenameSpec.scala → ...ala/chiselTests/naming/TypenameSpec.scala b/...a-2/chiselTests/naming/TypenameSpec.scala → ...ala/chiselTests/naming/TypenameSpec.scala
diff --git a/...elTests/stage/ChiselAnnotationsSpec.scala → ...elTests/stage/ChiselAnnotationsSpec.scala b/...elTests/stage/ChiselAnnotationsSpec.scala → ...elTests/stage/ChiselAnnotationsSpec.scala
@@ -8,6 +8,7 @@ import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, Design
 import firrtl.options.OptionsException
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 
 class ChiselAnnotationsSpecFoo extends RawModule {
   val in = IO(Input(Bool()))

diff --git a/...AddImplicitOutputAnnotationFileSpec.scala → ...AddImplicitOutputAnnotationFileSpec.scala b/...AddImplicitOutputAnnotationFileSpec.scala → ...AddImplicitOutputAnnotationFileSpec.scala
@@ -6,7 +6,7 @@ import chisel3.RawModule
 import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{AddImplicitOutputAnnotationFile, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{OutputAnnotationFileAnnotation, Phase}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers

diff --git a/...ge/phases/AddImplicitOutputFileSpec.scala → ...ge/phases/AddImplicitOutputFileSpec.scala b/...ge/phases/AddImplicitOutputFileSpec.scala → ...ge/phases/AddImplicitOutputFileSpec.scala
@@ -6,7 +6,7 @@ import chisel3.RawModule
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation}
 import chisel3.stage.phases.{AddImplicitOutputFile, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Phase, StageOptions, TargetDirAnnotation}
 import firrtl.options.Viewer.view
 import org.scalatest.flatspec.AnyFlatSpec

diff --git a/...ses/AddSerializationAnnotationsSpec.scala → ...ses/AddSerializationAnnotationsSpec.scala b/...ses/AddSerializationAnnotationsSpec.scala → ...ses/AddSerializationAnnotationsSpec.scala
@@ -7,7 +7,7 @@ import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation, Cir
 import chisel3.stage.CircuitSerializationAnnotation._
 import chisel3.stage.phases.{AddImplicitOutputFile, AddSerializationAnnotations, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Dependency, Phase, PhaseManager, TargetDirAnnotation}
 import firrtl.options.Viewer.view
 import org.scalatest.flatspec.AnyFlatSpec