Fix BoringUtils for identity views

chipsalliance · Jun 26, 2024 · 73824c4 · 73824c4
1 parent 2c5e185
commit 73824c4
Show file tree

Hide file tree

Showing 2 changed files with 61 additions and 1 deletion.
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
@@ -225,7 +225,12 @@ abstract class RawModule extends BaseModule {
   }
   private[chisel3] val stagedSecretCommands = collection.mutable.ArrayBuffer[Command]()
 
-  private[chisel3] def secretConnection(left: Data, right: Data)(implicit si: SourceInfo): Unit = {
+  private[chisel3] def secretConnection(left: Data, _right: Data)(implicit si: SourceInfo): Unit = {
+    val (right: Data, _) = chisel3.experimental.dataview
+      .reifyIdentityView(_right)
+      .getOrElse(
+        throwException(s"BoringUtils currently only support identity views, ${_right} has multiple targets.")
+      )
     val rhs = (left.probeInfo.nonEmpty, right.probeInfo.nonEmpty) match {
       case (true, true)                                 => ProbeDefine(si, left.lref, Node(right))
       case (true, false) if left.probeInfo.get.writable => ProbeDefine(si, left.lref, RWProbeExpr(Node(right)))

diff --git a/src/test/scala/chiselTests/BoringUtilsTapSpec.scala b/src/test/scala/chiselTests/BoringUtilsTapSpec.scala
@@ -165,6 +165,32 @@ class BoringUtilsTapSpec extends ChiselFlatSpec with ChiselRunners with Utils wi
     )()
   }
 
+  it should "work for identity views" in {
+    import chisel3.experimental.dataview._
+    class Foo extends RawModule {
+      private val internalWire = Wire(Bool())
+      val view = internalWire.viewAs[Bool]
+    }
+    class Top extends RawModule {
+      val foo = Module(new Foo())
+      val outProbe = IO(probe.Probe(Bool()))
+      val out = IO(Bool())
+      probe.define(outProbe, BoringUtils.tap(foo.view))
+      out := BoringUtils.tapAndRead(foo.view)
+    }
+    val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Top)
+    matchesAndOmits(chirrtl)(
+      "module Foo :",
+      "output bore : Probe<UInt<1>>",
+      "output out_bore : Probe<UInt<1>>",
+      "define bore = probe(internalWire)",
+      "define out_bore = probe(internalWire)",
+      "module Top :",
+      "define outProbe = foo.bore",
+      "connect out, read(foo.out_bore)"
+    )()
+  }
+
   "Writable tap" should "work downwards from grandparent to grandchild" in {
     class Bar extends RawModule {
       val internalWire = Wire(Bool())
@@ -527,4 +553,33 @@ class BoringUtilsTapSpec extends ChiselFlatSpec with ChiselRunners with Utils wi
     )()
   }
 
+  it should "work for identity views" in {
+    import chisel3.experimental.dataview._
+    class Bar extends RawModule {
+      private val internalWire = Wire(Bool())
+      val view = internalWire.viewAs[Bool]
+    }
+    class Foo extends RawModule {
+      val bar = Module(new Bar)
+    }
+    class Top extends RawModule {
+      val foo = Module(new Foo)
+      val out = IO(Bool())
+      out := probe.read(BoringUtils.rwTap(foo.bar.view))
+      probe.forceInitial(BoringUtils.rwTap(foo.bar.view), false.B)
+    }
+    val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Top)
+    matchesAndOmits(chirrtl)(
+      "module Bar :",
+      "output out_bore : RWProbe<UInt<1>>",
+      "define out_bore = rwprobe(internalWire)",
+      "module Foo :",
+      "output out_bore : RWProbe<UInt<1>>",
+      "define out_bore = bar.out_bore",
+      "module Top :",
+      "connect out, read(foo.out_bore)",
+      "force_initial(foo.bore, UInt<1>(0h0))"
+    )()
+  }
+
 }