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RV32IM Pipelined Processor Design

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Team

• E/20/032, Bandara A.M.N.C., [email protected]
• E/20/034, Bandara G.M.M.R., [email protected]
• E/20/157, Janakantha S.M.B.G., [email protected]

Abstract

This project focuses on the design and implementation of a custom 32-bit RISC-V processor supporting the RV32IM instruction set architecture (ISA). Developed as part of the Advanced Computer Architecture course (CO502), the processor encompasses essential features of the RISC-V standard, including integer operations (RV32I) and multiplication/division (M extension).

Key objectives include creating a modular, Verilog-based design with a pipelined architecture to optimize performance. The project will also incorporate testing and verification using simulation tools to ensure accuracy and compliance with the RISC-V specification.

This repository will serve as a collaborative platform to document progress, manage code, and host design files, test benches, and reports. By the project's conclusion, a fully functional RV32IM processor will be available, showcasing an efficient and robust processor design tailored for educational and experimental purposes.