co502 RV32IM pipeline implementation group 2

This Git repository contains the implementation of a RISC32IM processor pipeline using Verilog. The pipeline includes stages for instruction fetch, decode, execute, memory access, and write-back. The implementation includes a testbench for verification.

Team Members:

1. E/20/419 - Wakkumbura M.M.S.S. , [email protected]
2. E/20/439 - Wickramasinghe J.M.W.G.R.L. , [email protected]
3. E/20/036 - Bandara K.G.R.I , [email protected]

Project Supervisors:

1. Dr. Isuru Nawinne , [email protected]