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Fixed SME index alias printing issue. #1925

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Merged
kabeor merged 4 commits into from
Oct 24, 2022
Merged

Fixed SME index alias printing issue. #1925

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0880fb3
Fixed SME index alias printing issue.
FinnWilkinson Oct 11, 2022
fa060ec
Fixed for loop initial declaration errors in AArch64InstPrinter.
FinnWilkinson Oct 12, 2022
a4d7b7f
Added test for issue 1924.
FinnWilkinson Oct 24, 2022
6225717
Updated suite/cstest/arm64_detail to work with SVCR and SME_INDEX ope…
FinnWilkinson Oct 24, 2022
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15 changes: 13 additions & 2 deletions arch/AArch64/AArch64GenAsmWriter.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -26277,6 +26277,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
++I;
}

bool isSME = false;
do {
if (AsmString[I] == '$') {
++I;
Expand All @@ -26289,9 +26290,19 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS);
} else {
if (AsmString[I] == '[') {
set_mem_access(MI, true);
if (AsmString[I-1] != ' '){
set_sme_index(MI, true);
isSME = true;
} else {
set_mem_access(MI, true);
}
} else if (AsmString[I] == ']') {
set_mem_access(MI, false);
if (isSME) {
set_sme_index(MI, false);
isSME = false;
} else {
set_mem_access(MI, false);
}
}
SStream_concat1(OS, AsmString[I++]);
}
Expand Down
28 changes: 13 additions & 15 deletions arch/AArch64/AArch64InstPrinter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -898,12 +898,10 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
if(MI->csh->detail){
MI->flat_insn->detail->arm64.op_count = 2;
#ifndef CAPSTONE_DIET
for (int i = 0; i < 2; i++)
{
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access =
get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
MI->ac_idx++;
}
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
MI->ac_idx++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm64.operands[0].type = ARM64_OP_SVCR;
MI->flat_insn->detail->arm64.operands[0].sys = (unsigned)ARM64_SYSREG_SVCR;
Expand Down Expand Up @@ -2488,8 +2486,8 @@ static void printMatrixTileVector(MCInst *MI, unsigned OpNum, SStream *O, bool I
const size_t strLn = strlen(RegName);
// +2 for extra chars, + 1 for null char \0
char *RegNameNew = malloc(sizeof(char) * (strLn + 2 + 1));
int index = 0;
for(int i = 0; i < (strLn + 2); i++){
int index = 0, i;
for (i = 0; i < (strLn + 2); i++){
if(RegName[i] != '.'){
RegNameNew[index] = RegName[i];
index++;
Expand Down Expand Up @@ -2527,18 +2525,18 @@ static void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O){
unsigned MaxRegs = 8;
unsigned RegMask = MCOperand_getImm(MCInst_getOperand(MI, OpNum));

unsigned NumRegs = 0;
for (unsigned I = 0; I < MaxRegs; ++I)
unsigned NumRegs = 0, I;
for (I = 0; I < MaxRegs; ++I)
if ((RegMask & (1 << I)) != 0)
++NumRegs;

SStream_concat0(O, "{");
unsigned Printed = 0;
for (unsigned I = 0; I < MaxRegs; ++I) {
unsigned Reg = RegMask & (1 << I);
unsigned Printed = 0, J;
for (J = 0; J < MaxRegs; ++J) {
unsigned Reg = RegMask & (1 << J);
if (Reg == 0)
continue;
SStream_concat0(O, getRegisterName(MatrixZADRegisterTable[I], AArch64_NoRegAltName));
SStream_concat0(O, getRegisterName(MatrixZADRegisterTable[J], AArch64_NoRegAltName));

if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
Expand All @@ -2550,7 +2548,7 @@ static void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O){
#endif

MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MatrixZADRegisterTable[I];
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MatrixZADRegisterTable[J];
MI->flat_insn->detail->arm64.op_count++;
}

Expand Down
4 changes: 4 additions & 0 deletions suite/cstest/issues.cs
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Original file line number Diff line number Diff line change
@@ -1,3 +1,7 @@
!# issue 1924 SME Index instruction alias printing is not always valid
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x02,0x00,0x9f,0xe0 == ld1w {za0h.s[w12, 2]}, p0/z, [x0] ; operands[0].type: REG = zas0 ; operands[0].index.base: REG = w12 ; operands[0].index.disp: 0x2 ; operands[1].type: REG = p0 ; operands[2].type: MEM ; operands[2].mem.base: REG = x0

!# issue 1912 PPC register name
!# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, None
0x2d,0x03,0x00,0x80 == cmpwi cr2, r3, 0x80
Expand Down
16 changes: 16 additions & 0 deletions suite/cstest/src/arm64_detail.c
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Original file line number Diff line number Diff line change
Expand Up @@ -74,6 +74,22 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
case ARM64_OP_BARRIER:
add_str(&result, " ; operands[%u].type: BARRIER = 0x%x", i, op->barrier);
break;
case ARM64_OP_SME_INDEX:
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->sme_index.reg));
if(op->sme_index.base != ARM64_REG_INVALID)
add_str(&result, " ; operands[%u].index.base: REG = %s", i, cs_reg_name(*handle, op->sme_index.base));
if(op->sme_index.disp != 0)
add_str(&result, " ; operands[%u].index.disp: 0x%x", i, op->sme_index.disp);
break;
case ARM64_OP_SVCR:
add_str(&result, " ; operands[%u].type: SYS = 0x%x", i, op->sys);
if(op->svcr == ARM64_SVCR_SVCRSM)
add_str(&result, " ; operands[%u].svcr: BIT = SM", i);
if(op->svcr == ARM64_SVCR_SVCRZA)
add_str(&result, " ; operands[%u].svcr: BIT = ZA", i);
if(op->svcr == ARM64_SVCR_SVCRSMZA)
add_str(&result, " ; operands[%u].svcr: BIT = SM & ZA", i);
break;
}

access = op->access;
Expand Down
15 changes: 13 additions & 2 deletions suite/synctools/asmwriter.py
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Original file line number Diff line number Diff line change
Expand Up @@ -768,6 +768,7 @@ def print_line(line):
++I;
}

bool isSME = false;
do {
if (AsmString[I] == '$') {
++I;
Expand All @@ -780,9 +781,19 @@ def print_line(line):
printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS);
} else {
if (AsmString[I] == '[') {
set_mem_access(MI, true);
if (AsmString[I-1] != ' ') {
set_sme_index(MI, true);
isSME = true;
} else {
set_mem_access(MI, true);
}
} else if (AsmString[I] == ']') {
set_mem_access(MI, false);
if (isSME) {
set_sme_index(MI, false);
isSME = false;
} else {
set_mem_access(MI, false);
}
}
SStream_concat1(OS, AsmString[I++]);
}
Expand Down