Refactor after rebase

capstone-engine · Aug 6, 2023 · fda1de3 · fda1de3
1 parent 862926a
commit fda1de3
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Showing 28 changed files with 515 additions and 7,766 deletions.
diff --git a/Mapping.c b/Mapping.c
@@ -313,6 +313,7 @@ DEFINE_get_detail_op(arm, ARM);
 DEFINE_get_detail_op(ppc, PPC);
 DEFINE_get_detail_op(tricore, TriCore);
 DEFINE_get_detail_op(aarch64, AArch64);
+DEFINE_get_detail_op(alpha, Alpha);
 
 /// Returns true if for this architecture the
 /// alias operands should be filled.

diff --git a/Mapping.h b/Mapping.h
@@ -145,6 +145,8 @@ DEFINE_inc_detail_op_count(tricore, TriCore);
 DEFINE_dec_detail_op_count(tricore, TriCore);
 DEFINE_inc_detail_op_count(aarch64, AArch64);
 DEFINE_dec_detail_op_count(aarch64, AArch64);
+DEFINE_inc_detail_op_count(alpha, Alpha);
+DEFINE_dec_detail_op_count(alpha, Alpha);
 
 /// Returns true if a memory operand is currently edited.
 static inline bool doing_mem(const MCInst *MI)
@@ -170,6 +172,7 @@ DEFINE_get_arch_detail(arm, ARM);
 DEFINE_get_arch_detail(ppc, PPC);
 DEFINE_get_arch_detail(tricore, TriCore);
 DEFINE_get_arch_detail(aarch64, AArch64);
+DEFINE_get_arch_detail(alpha, Alpha);
 
 static inline bool detail_is_set(const MCInst *MI)
 {
@@ -209,61 +212,4 @@ bool map_use_alias_details(const MCInst *MI);
 
 void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size);
 
-/// Increments the detail->arch.op_count by one.
-#define DEFINE_inc_detail_op_count(arch, ARCH)                                 \
-	static inline void ARCH##_inc_op_count(MCInst *MI)                         \
-	{                                                                          \
-		MI->flat_insn->detail->arch.op_count++;                                \
-	}
-
-/// Decrements the detail->arch.op_count by one.
-#define DEFINE_dec_detail_op_count(arch, ARCH)                                 \
-	static inline void ARCH##_dec_op_count(MCInst *MI)                         \
-	{                                                                          \
-		MI->flat_insn->detail->arch.op_count--;                                \
-	}
-
-DEFINE_inc_detail_op_count(arm, ARM);
-DEFINE_dec_detail_op_count(arm, ARM);
-DEFINE_inc_detail_op_count(ppc, PPC);
-DEFINE_dec_detail_op_count(ppc, PPC);
-DEFINE_inc_detail_op_count(aarch64, AArch64);
-DEFINE_dec_detail_op_count(aarch64, AArch64);
-DEFINE_inc_detail_op_count(alpha, Alpha);
-DEFINE_dec_detail_op_count(alpha, Alpha);
-
-/// Returns true if a memory operand is currently edited.
-static inline bool doing_mem(const MCInst *MI) { return MI->csh->doing_mem; }
-
-/// Sets the doing_mem flag to @status.
-static inline void set_doing_mem(const MCInst *MI, bool status)
-{
-	MI->csh->doing_mem = status;
-}
-
-/// Returns detail->arch
-#define DEFINE_get_arch_detail(arch, ARCH)                                     \
-	static inline cs_##arch *ARCH##_get_detail(const MCInst *MI)               \
-	{                                                                          \
-		assert(MI && MI->flat_insn && MI->flat_insn->detail);                  \
-		return &MI->flat_insn->detail->arch;                                   \
-	}
-
-DEFINE_get_arch_detail(arm, ARM);
-DEFINE_get_arch_detail(ppc, PPC);
-DEFINE_get_arch_detail(aarch64, AArch64);
-DEFINE_get_arch_detail(alpha, Alpha);
-
-static inline bool detail_is_set(const MCInst *MI)
-{
-	assert(MI && MI->flat_insn);
-	return MI->flat_insn->detail != NULL;
-}
-
-static inline cs_detail *get_detail(const MCInst *MI)
-{
-	assert(MI && MI->flat_insn);
-	return MI->flat_insn->detail;
-}
-
 #endif // CS_MAPPING_H
diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc
@@ -18007,10 +18007,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
     // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane
     printVRegOperand(MI, 3, O);
     break;
-  case 53:
-    // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane
-    printVRegOperand(MI, 3, O);
-    break;
   case 54:
     // LD1B_2Z, LD1B_2Z_IMM, LD1B_4Z, LD1B_4Z_IMM, LD1B_VG2_M2ZPXI, LD1B_VG2_...
     printPredicateAsCounter_0(MI, 1, O);
@@ -33962,23 +33958,23 @@ static bool AArch64InstPrinterValidateMCOperand(const MCOperand *MCOp,
     break;
   case 1: {
 
-    if (!MCOp.isImm())
+    if (!MCOperand_isImm(MCOp))
       return false;
     int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
     return AArch64_AM_isSVEMaskOfIdenticalElements_int8_t(Val);
 
     }
   case 2: {
 
-    if (!MCOp.isImm())
+    if (!MCOperand_isImm(MCOp))
       return false;
     int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
     return AArch64_AM_isSVEMaskOfIdenticalElements_int16_t(Val);
 
     }
   case 3: {
 
-    if (!MCOp.isImm())
+    if (!MCOperand_isImm(MCOp))
       return false;
     int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
     return AArch64_AM_isSVEMaskOfIdenticalElements_int32_t(Val);
@@ -33993,7 +33989,7 @@ static bool AArch64InstPrinterValidateMCOperand(const MCOperand *MCOp,
     }
   case 5: {
 
-    if (!MCOp.isImm())
+    if (!MCOperand_isImm(MCOp))
       return false;
     int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
     return AArch64_AM_isSVEMaskOfIdenticalElements_int16_t(Val) &&
@@ -34002,7 +33998,7 @@ static bool AArch64InstPrinterValidateMCOperand(const MCOperand *MCOp,
     }
   case 6: {
 
-    if (!MCOp.isImm())
+    if (!MCOperand_isImm(MCOp))
       return false;
     int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
     return AArch64_AM_isSVEMaskOfIdenticalElements_int32_t(Val) &&
@@ -34011,7 +34007,7 @@ static bool AArch64InstPrinterValidateMCOperand(const MCOperand *MCOp,
     }
   case 7: {
 
-    if (!MCOp.isImm())
+    if (!MCOperand_isImm(MCOp))
       return false;
     int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
     return AArch64_AM_isSVEMaskOfIdenticalElements_int64_t(Val) &&
@@ -34021,7 +34017,7 @@ static bool AArch64InstPrinterValidateMCOperand(const MCOperand *MCOp,
   case 8: {
 
     // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields.
-    if (!MCOp.isImm())
+    if (!MCOperand_isImm(MCOp))
       return false;
     return AArch64BTIHint_lookupBTIByEncoding(MCOperand_getImm(MCOp) ^ 32) != NULL;
 
@@ -34030,7 +34026,7 @@ static bool AArch64InstPrinterValidateMCOperand(const MCOperand *MCOp,
 
     // Check, if operand is valid, to fix exhaustive aliasing in disassembly.
     // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
-    if (!MCOp.isImm())
+    if (!MCOperand_isImm(MCOp))
       return false;
     return AArch64PSBHint_lookupPSBByEncoding(MCOperand_getImm(MCOp)) != NULL;
 

diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
@@ -2237,7 +2237,6 @@ void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
 		printUInt32Bang(O, Val);
 		SStream_concat0(O, markup(">"));
 	}
-	SStream_concat0(O, " }");
 }
 
 void printBarriernXSOption(MCInst *MI, unsigned OpNo, SStream *O)

diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h
@@ -65,18 +65,4 @@ void AArch64_set_detail_shift_ext(MCInst *MI, unsigned OpNum, bool SignExtend,
 void AArch64_set_detail_op_float(MCInst *MI, unsigned OpNum, float Val);
 void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op, aarch64_op_type type);
 
-void AArch64_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
-					   va_list args);
-
-static inline void add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
-								 ...)
-{
-	if (!MI->flat_insn->detail)
-		return;
-	va_list args;
-	va_start(args, op_group);
-	AArch64_add_cs_detail(MI, op_group, args);
-	va_end(args);
-}
-
 #endif
diff --git a/arch/ARM/ARMAddressingModes.h b/arch/ARM/ARMAddressingModes.h
@@ -7,7 +7,7 @@
 /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
 
 /* Only small edits allowed. */
-/* For multiple similar edits, please create a Patch for the translator. */
+/* For multiple similiar edits, please create a Patch for the translator. */
 
 /* Capstone's C++ file translator: */
 /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
@@ -38,9 +38,6 @@
 #define CONCAT(a, b) CONCAT_(a, b)
 #define CONCAT_(a, b) a##_##b
 
-#define CONCAT(a, b) CONCAT_(a, b)
-#define CONCAT_(a, b) a##_##b
-
 /// ARM_AM - ARM Addressing Mode Stuff
 typedef enum ShiftOpc {
 	ARM_AM_no_shift = 0,
@@ -152,7 +149,10 @@ static inline unsigned ARM_AM_getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
 	return ShOp | (Imm << 3);
 }
 
-static inline unsigned ARM_AM_getSORegOffset(unsigned Op) { return Op >> 3; }
+static inline unsigned ARM_AM_getSORegOffset(unsigned Op)
+{
+	return Op >> 3;
+}
 
 static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
 {

diff --git a/arch/ARM/ARMBaseInfo.c b/arch/ARM/ARMBaseInfo.c
@@ -7,7 +7,7 @@
 /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
 
 /* Only small edits allowed. */
-/* For multiple similar edits, please create a Patch for the translator. */
+/* For multiple similiar edits, please create a Patch for the translator. */
 
 /* Capstone's C++ file translator: */
 /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */