sync with LLVM 7.0.1. X86 is first

CMakeLists.txt

@@ -268,6 +268,7 @@ if (CAPSTONE_X86_SUPPORT)
         arch/X86/X86Disassembler.c
         arch/X86/X86DisassemblerDecoder.c
         arch/X86/X86IntelInstPrinter.c
+        arch/X86/X86InstPrinterCommon.c
         arch/X86/X86Mapping.c
         arch/X86/X86Module.c
     )

LEB128.h

@@ -13,7 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #ifndef CS_LLVM_SUPPORT_LEB128_H
 #define CS_LLVM_SUPPORT_LEB128_H

MCDisassembler.h

@@ -1,5 +1,5 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #ifndef CS_MCDISASSEMBLER_H
 #define CS_MCDISASSEMBLER_H

MCFixedLenDisassembler.h

@@ -10,7 +10,7 @@
 //===----------------------------------------------------------------------===//
 
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
 #define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
@@ -23,6 +23,8 @@ enum DecoderOps {
 							  //                uleb128 Val, uint16_t NumToSkip)
 	MCD_OPC_CheckPredicate,   // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip)
 	MCD_OPC_Decode,           // OPC_Decode(uleb128 Opcode, uleb128 DIdx)
+	MCD_OPC_TryDecode,        // OPC_TryDecode(uleb128 Opcode, uleb128 DIdx,
+                              //               uint16_t NumToSkip)
 	MCD_OPC_SoftFail,         // OPC_SoftFail(uleb128 PMask, uleb128 NMask)
 	MCD_OPC_Fail              // OPC_Fail()
 };

MCInst.c

@@ -1,5 +1,5 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #if defined(CAPSTONE_HAS_OSXKERNEL)
 #include <Availability.h>

MCInst.h

@@ -14,7 +14,7 @@
 //===----------------------------------------------------------------------===//
 
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #ifndef CS_MCINST_H
 #define CS_MCINST_H
@@ -97,6 +97,11 @@ struct MCInst {
 	cs_struct *csh;	// save the main csh
 	uint8_t x86opsize;	// opsize for [mem] operand
 
+	// These flags could be used to pass some info from one target subcomponent
+	// to another, for example, from disassembler to asm printer. The values of
+	// the flags have any sense on target level only (e.g. prefixes on x86).
+	unsigned flags;
+
 	// (Optional) instruction prefix, which can be up to 4 bytes.
 	// A prefix byte gets value 0 when irrelevant.
 	// This is copied from cs_x86 struct

MCInstrDesc.c

@@ -1,5 +1,5 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #include "MCInstrDesc.h"
 

MCInstrDesc.h

@@ -13,11 +13,12 @@
 //===----------------------------------------------------------------------===//
 
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #ifndef CS_LLVM_MC_MCINSTRDESC_H
 #define CS_LLVM_MC_MCINSTRDESC_H
 
+#include "MCRegisterInfo.h"
 #include "capstone/platform.h"
 
 //===----------------------------------------------------------------------===//
@@ -41,32 +42,43 @@ enum MCOI_OperandFlags {
 
 /// Operand Type - Operands are tagged with one of the values of this enum.
 enum MCOI_OperandType {
-	MCOI_OPERAND_UNKNOWN,
-	MCOI_OPERAND_IMMEDIATE,
-	MCOI_OPERAND_REGISTER,
-	MCOI_OPERAND_MEMORY,
-	MCOI_OPERAND_PCREL
+	MCOI_OPERAND_UNKNOWN = 0,
+	MCOI_OPERAND_IMMEDIATE = 1,
+	MCOI_OPERAND_REGISTER = 2,
+	MCOI_OPERAND_MEMORY = 3,
+	MCOI_OPERAND_PCREL = 4,
+
+	MCOI_OPERAND_FIRST_GENERIC = 6,
+	MCOI_OPERAND_GENERIC_0 = 6,
+	MCOI_OPERAND_GENERIC_1 = 7,
+	MCOI_OPERAND_GENERIC_2 = 8,
+	MCOI_OPERAND_GENERIC_3 = 9,
+	MCOI_OPERAND_GENERIC_4 = 10,
+	MCOI_OPERAND_GENERIC_5 = 11,
+	MCOI_OPERAND_LAST_GENERIC = 11,
+
+	MCOI_OPERAND_FIRST_TARGET = 12,
 };
 
 
 /// MCOperandInfo - This holds information about one operand of a machine
 /// instruction, indicating the register class for register operands, etc.
 ///
 typedef struct MCOperandInfo {
-	/// RegClass - This specifies the register class enumeration of the operand
+	/// This specifies the register class enumeration of the operand
 	/// if the operand is a register.  If isLookupPtrRegClass is set, then this is
 	/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
 	/// get a dynamic register class.
 	int16_t RegClass;
 
-	/// Flags - These are flags from the MCOI::OperandFlags enum.
+	/// These are flags from the MCOI::OperandFlags enum.
 	uint8_t Flags;
 
-	/// OperandType - Information about the type of the operand.
+	/// Information about the type of the operand.
 	uint8_t OperandType;
 
-	/// Lower 16 bits are used to specify which constraints are set. The higher 16
-	/// bits are used to specify the value of constraints (4 bits each).
+	/// The lower 16 bits are used to specify which constraints are set.
+	/// The higher 16 bits are used to specify the value of constraints (4 bits each).
 	uint32_t Constraints;
 	/// Currently no other information.
 } MCOperandInfo;
@@ -77,8 +89,8 @@ typedef struct MCOperandInfo {
 //===----------------------------------------------------------------------===//
 
 /// MCInstrDesc flags - These should be considered private to the
-/// implementation of the MCInstrDesc class.  Clients should use the predicate
-/// methods on MCInstrDesc, not use these directly.  These all correspond to
+/// implementation of the MCInstrDesc class. Clients should use the predicate
+/// methods on MCInstrDesc, not use these directly. These all correspond to
 /// bitfields in the MCInstrDesc::Flags field.
 enum {
 	MCID_Variadic = 0,
@@ -92,6 +104,7 @@ enum {
 	MCID_IndirectBranch,
 	MCID_Compare,
 	MCID_MoveImm,
+	MCID_MoveReg,
 	MCID_Bitcast,
 	MCID_Select,
 	MCID_DelaySlot,
@@ -111,12 +124,15 @@ enum {
 	MCID_ExtraDefRegAllocReq,
 	MCID_RegSequence,
 	MCID_ExtractSubreg,
-	MCID_InsertSubreg
+	MCID_InsertSubreg,
+	MCID_Convergent,
+	MCID_Add,
+	MCID_Trap,
 };
 
 /// MCInstrDesc - Describe properties that are true of each instruction in the
-/// target description file.  This captures information about side effects,
-/// register use and many other things.  There is one instance of this struct
+/// target description file. This captures information about side effects,
+/// register use and many other things. There is one instance of this struct
 /// for each target instruction class, and the MachineInstr class points to
 /// this struct directly to describe itself.
 typedef struct MCInstrDesc {

MCRegisterInfo.c

@@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #include "MCRegisterInfo.h"
 

MCRegisterInfo.h

@@ -14,7 +14,7 @@
 //===----------------------------------------------------------------------===//
 
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #ifndef CS_LLVM_MC_MCREGISTERINFO_H
 #define CS_LLVM_MC_MCREGISTERINFO_H
@@ -36,9 +36,7 @@ typedef struct MCRegisterClass {
 /// register.  The SubRegs field is a zero terminated array of registers that
 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
 /// of AX. The SuperRegs field is a zero terminated array of registers that are
-/// super-registers of the specific register, e.g. RAX, EAX, are
 /// super-registers of AX.
-///
 typedef struct MCRegisterDesc {
 	uint32_t Name;      // Printable name for the reg (for debugging)
 	uint32_t SubRegs;   // Sub-register set, described above
@@ -54,7 +52,7 @@ typedef struct MCRegisterDesc {
 
 	/// Index into list with lane mask sequences. The sequence contains a lanemask
 	/// for every register unit.
-	uint16_t RegUnitLaneMasks;
+	uint16_t RegUnitLaneMasks;	// ???
 } MCRegisterDesc;
 
 /// MCRegisterInfo base class - We assume that the target defines a static
@@ -68,7 +66,6 @@ typedef struct MCRegisterDesc {
 /// specialize this class. MCRegisterInfo should only contain getters to access
 /// TableGen generated physical register data. It must not be extended with
 /// virtual methods.
-///
 typedef struct MCRegisterInfo {
 	const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
 	unsigned NumRegs;                           // Number of entries in the array
@@ -79,7 +76,9 @@ typedef struct MCRegisterInfo {
 	unsigned NumRegUnits;                       // Number of regunits.
 	uint16_t (*RegUnitRoots)[2];          // Pointer to regunit root table.
 	const MCPhysReg *DiffLists;                 // Pointer to the difflists array
+	// const LaneBitmask *RegUnitMaskSequences;    // Pointer to lane mask sequences
 	const char *RegStrings;                     // Pointer to the string table.
+	// const char *RegClassStrings;                // Pointer to the class strings.
 	const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
 	// array.
 	unsigned NumSubRegIndices;                  // Number of subreg indices.

Makefile

@@ -179,21 +179,16 @@ X86_REDUCE = _reduce
 CFLAGS += -DCAPSTONE_X86_REDUCE -Os
 endif
 
+
 DEP_X86 =
-DEP_X86 += arch/X86/X86GenAsmWriter$(X86_REDUCE).inc
-DEP_X86 += arch/X86/X86GenAsmWriter1$(X86_REDUCE).inc
-DEP_X86 += arch/X86/X86GenDisassemblerTables$(X86_REDUCE).inc
-DEP_X86 += arch/X86/X86GenInstrInfo$(X86_REDUCE).inc
-DEP_X86 += arch/X86/X86GenRegisterInfo.inc
-DEP_X86 += arch/X86/X86MappingInsn$(X86_REDUCE).inc
-DEP_X86 += arch/X86/X86MappingInsnOp$(X86_REDUCE).inc
-DEP_X86 += arch/X86/X86ImmSize.inc
+DEP_X86 += $(wildcard arch/X86/X86*.inc)
 
 LIBOBJ_X86 =
 ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_X86
 	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o
 	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o
+    LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86InstPrinterCommon.o
 	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o
 # assembly syntax is irrelevant in Diet mode, when this info is suppressed
 ifeq (,$(findstring yes,$(CAPSTONE_DIET)))

MathExtras.h

@@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H
 #define CS_LLVM_SUPPORT_MATHEXTRAS_H

SStream.c

@@ -1,5 +1,5 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #include <stdarg.h>
 #if defined(CAPSTONE_HAS_OSXKERNEL)
@@ -45,9 +45,6 @@ void SStream_concat(SStream *ss, const char *fmt, ...)
 	va_list ap;
 	int ret;
 
-	if (ss->index >= sizeof(ss->buffer)) {
-		return;
-	}
 	va_start(ap, fmt);
 	ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
 	va_end(ap);

SStream.h

@@ -1,5 +1,5 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
 
 #ifndef CS_SSTREAM_H_
 #define CS_SSTREAM_H_