Implement AOT support for RISCV #649

no1wudi · 2021-06-07T06:22:03Z

No description provided.

no1wudi · 2021-06-07T07:05:30Z

Now native code generation seem works by emit native object file, we still need to implement relocation logic for riscv platform.

wenyongh · 2021-06-07T07:48:29Z

Now native code generation seem works by emit native object file, we still need to implement relocation logic for riscv platform.

Yes, so could you please add file aot_reloc_riscv32.c and aot_reloc_riscv64.c under core/iwasm/aot/arch/ to implement the relocation? If some relocation types are not easy to implement, we can work together to resolve them.

no1wudi · 2021-06-07T08:22:45Z

Yes, so could you please add file aot_reloc_riscv32.c and aot_reloc_riscv64.c under core/iwasm/aot/arch/ to implement the relocation? If some relocation types are not easy to implement, we can work together to resolve them.

@wenyongh OK, and we can merge the invokeNative riscv32/riscv64 version into one since they share the common ISA except width of register like this: https://github.com/zephyrproject-rtos/zephyr/blob/1f0b783bbb2cd0546d0fee12d72cccc694847915/include/arch/riscv/arch.h#L190

wenyongh · 2021-06-07T08:31:50Z

Yes, so could you please add file aot_reloc_riscv32.c and aot_reloc_riscv64.c under core/iwasm/aot/arch/ to implement the relocation? If some relocation types are not easy to implement, we can work together to resolve them.

@wenyongh OK, and we can merge the invokeNative riscv32/riscv64 version into one since they share the common ISA except width of register like this: https://github.com/zephyrproject-rtos/zephyr/blob/1f0b783bbb2cd0546d0fee12d72cccc694847915/include/arch/riscv/arch.h#L190

Should be aot_reloc_riscv.c? OK, it is good to use only one file.

no1wudi · 2021-06-07T08:40:07Z

Should be aot_reloc_riscv.c? OK, it is good to use only one file.

Yes, and we should merge these files into invokeNattive_riscv.s:

invokeNative_riscv32_ilp32.s
invokeNative_riscv32_ilp32d.s
invokeNative_riscv32_ilp64.s
invokeNative_riscv32_ilp32d.s

@wenyongh I've add a new file invokeNative_riscv.S, tested with rv32 imac, could you do some tests on other risc v platform? Then we can remove files above.

wenyongh

Should remove the original .s files and change the related make files?

core/iwasm/common/arch/invokeNative_riscv.S

no1wudi · 2021-06-16T10:02:49Z

core/iwasm/aot/arch/aot_reloc_riscv.c

+    switch (reloc_type) {
+        case R_RISCV_CALL:
+            /* lui  t0, hi20 */
+            *(uint32 *)(P + 0) = (uint32)hi20 | 0x2b7;


Potential bugs here since we use absolute address to jump, it works fine on rv32, but on rv64 platform, target address may exceed the 32bit (4GB) address space.

Please take a look @wenyongh

Yes, should add check, like R_X86_64_PC32/R_X86_64_32/R_X86_64_32S in aot_reloc_x86_64.c. Seems that here we should check whether (uint32)(uintptr_t)symbol_addr == (uintptr_t)symbol_addr?

If exceeds 4G, had better prompt using --size-level=1 if it fixes the issue.
And in aot_loader.c, try adding MMAP_MAP_32BIT for mmap:

#if defined(BUILD_TARGET_X86_64) || defined(BUILD_TARGET_AMD_64) \ || defined(BUILD_TARGET_RISCV64) /* aot code and data in x86_64 must be in range 0 to 2G due to relocation for R_X86_64_32/32S/PC32 */ int map_flags = MMAP_MAP_32BIT; #else int map_flags = MMAP_MAP_NONE; #endif

OK. Not sure whether there is only one relocation type needed to implement. Do you want to merge to patch firstly, and then test the spec cases and some standalone cases, or test the spec cases firstly, implement all the relocation types and then merge the patch?

I prefer to implement all relocation types step by step since R_RISCV_CALL meet the requirements of our current workload.

Will this block the next release?

It is OK, we had better test more cases, not sure whether your riscv hardware can run Linux system? If not, you can enable the QEMU to test them, ref to Fedora QEMU, and run it on Linux, the ABI is RISCV64_LP64D.

core/iwasm/aot/arch/aot_reloc_riscv.c

core/iwasm/aot/iwasm_aot.cmake

wenyongh · 2021-06-16T10:16:57Z

core/iwasm/aot/arch/aot_reloc_riscv.c

+    switch (reloc_type) {
+        case R_RISCV_CALL:
+            /* lui  t0, hi20 */
+            *(uint32 *)(P + 0) = (uint32)hi20 | 0x2b7;


Yes, should add check, like R_X86_64_PC32/R_X86_64_32/R_X86_64_32S in aot_reloc_x86_64.c. Seems that here we should check whether (uint32)(uintptr_t)symbol_addr == (uintptr_t)symbol_addr?

If exceeds 4G, had better prompt using --size-level=1 if it fixes the issue.
And in aot_loader.c, try adding MMAP_MAP_32BIT for mmap:

#if defined(BUILD_TARGET_X86_64) || defined(BUILD_TARGET_AMD_64) \ || defined(BUILD_TARGET_RISCV64) /* aot code and data in x86_64 must be in range 0 to 2G due to relocation for R_X86_64_32/32S/PC32 */ int map_flags = MMAP_MAP_32BIT; #else int map_flags = MMAP_MAP_NONE; #endif

core/iwasm/aot/arch/aot_reloc_riscv.c

core/iwasm/common/arch/invokeNative_riscv.S

core/iwasm/aot/aot_loader.c

wenyongh · 2021-06-17T04:59:01Z

core/iwasm/aot/arch/aot_reloc_riscv.c

+    switch (reloc_type) {
+        case R_RISCV_CALL:
+            /* lui  t0, hi20 */
+            *(uint32 *)(P + 0) = (uint32)hi20 | 0x2b7;


OK. Not sure whether there is only one relocation type needed to implement. Do you want to merge to patch firstly, and then test the spec cases and some standalone cases, or test the spec cases firstly, implement all the relocation types and then merge the patch?

core/iwasm/common/arch/invokeNative_riscv.S

product-mini/platforms/nuttx/wamr.mk

core/iwasm/aot/arch/aot_reloc_riscv.c

wenyongh · 2021-07-17T07:14:16Z

core/iwasm/aot/arch/aot_reloc_riscv.c

+
+        case R_RISCV_HI20:
+        {
+            long offset = (long)symbol_addr;


Should be (long)(symbol_addr + reloc_addend); //S + A

Same as above, shall we check whether S + A in range 0 - 2^20-1?

wenyongh · 2021-07-17T07:20:27Z

core/iwasm/aot/arch/aot_reloc_riscv.c

+
+        case R_RISCV_LO12_I:
+        {
+            long offset = (long)symbol_addr;


Same as above, (long)(symbol_addr + reloc_addend), and check whether S + A is in range 0 - 2^12-1?

wenyongh · 2021-07-17T07:21:09Z

core/iwasm/aot/arch/aot_reloc_riscv.c

+
+        case R_RISCV_LO12_S:
+        {
+            long offset = (long)symbol_addr;


Same as above, (long)(symbol_addr + reloc_addend), and check whether S + A is in range 0 - 2^12-1?

Signed-off-by: Huang Qi <[email protected]>

Implement more relocation types, re-org code and fix some issues

Merge pull request #3 from wenyongh/test/riscv_aot

Enable os_mmap with MAP_32BIT flag for riscv64

Implement AOT support for RISCV (#649)

Enable RISCV AOT support, the supported ABIs are LP64 and LP64D for riscv64, ILP32 and ILP32D for riscv32. For wamrc: use --target=riscv64/riscv32 to specify the target arch of output AOT file, use --target-abi=lp64d/lp64/ilp32d/ilp32 to specify the target ABI, if --target-abi isn't specified, by default lp64d is used for riscv64, and ilp32d is used for riscv32. Signed-off-by: Huang Qi <[email protected]> Co-authored-by: wenyongh <[email protected]>

no1wudi marked this pull request as draft June 7, 2021 06:22

no1wudi mentioned this pull request Jun 7, 2021

platform/nuttx: Support riscv based chips #648

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no1wudi force-pushed the main branch from 7f2bc52 to 641d77f Compare June 7, 2021 07:44

no1wudi force-pushed the main branch from bc1c0d5 to bb378bc Compare June 7, 2021 09:52

wenyongh reviewed Jun 7, 2021

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no1wudi force-pushed the main branch 5 times, most recently from 2d060fb to 2ec71ea Compare June 8, 2021 02:21

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no1wudi force-pushed the main branch from 2ec71ea to 8335ffa Compare June 8, 2021 05:29

no1wudi requested a review from wenyongh June 9, 2021 02:44

no1wudi marked this pull request as ready for review June 16, 2021 09:57

no1wudi commented Jun 16, 2021

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wenyongh reviewed Jun 16, 2021

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core/iwasm/aot/arch/aot_reloc_riscv.c Outdated Show resolved Hide resolved

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no1wudi force-pushed the main branch from 489b6ca to 3d90a21 Compare June 16, 2021 10:07

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no1wudi force-pushed the main branch from 3d90a21 to 17a3045 Compare June 16, 2021 14:58

no1wudi requested a review from wenyongh June 17, 2021 03:13

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no1wudi force-pushed the main branch 2 times, most recently from 415254e to deae428 Compare June 17, 2021 07:10

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no1wudi force-pushed the main branch from f80672a to afe0d5c Compare July 12, 2021 06:42

no1wudi requested a review from wenyongh July 15, 2021 01:31

Implement more relocation types, re-org code and fix some issues

3df5d30

wenyongh reviewed Jul 17, 2021

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no1wudi and others added 15 commits July 19, 2021 13:52

Enable RISCV support in LLVM

9792a19

Signed-off-by: Huang Qi <[email protected]>

Add target & target-abi for riscv to wamrc

b3f5979

Signed-off-by: Huang Qi <[email protected]>

Merge invokeNative for riscv32/64 into unified implementation

828633c

Signed-off-by: Huang Qi <[email protected]>

Remove discrete invokeNative_riscv_xxx.s for riscv

6402aa2

Signed-off-by: Huang Qi <[email protected]>

Add E_MACHINE_RISCV to aot loader

6bf72fb

Signed-off-by: Huang Qi <[email protected]>

Implement relocator for riscv

80b4f23

Signed-off-by: Huang Qi <[email protected]>

Fix FP offset in invokeNatvie for riscv

d5a95fc

Signed-off-by: Huang Qi <[email protected]>

Add AOT support for riscv on NuttX

666f1aa

Signed-off-by: Huang Qi <[email protected]>

Fix some issues of riscv-aot

ce8e149

Enable setting target-abi for riscv

c325728

Enable relocation for .sdata symbol

42b1ea8

Support R_RISCV_CALL_PLT for AOT

9b9353d

Signed-off-by: Huang Qi <[email protected]>

Support R_RISCV_HI20 for AOT

426c104

Signed-off-by: Huang Qi <[email protected]>

Support R_RISCV_LO12_I/S in AOT

02cac0a

Signed-off-by: Huang Qi <[email protected]>

Minor fix for code format and data type

139c5c4

Signed-off-by: Huang Qi <[email protected]>

no1wudi force-pushed the main branch from 4631d33 to 139c5c4 Compare July 19, 2021 05:53

no1wudi and others added 5 commits July 19, 2021 16:31

Merge pull request #3 from wenyongh/test/riscv_aot

421598c

Implement more relocation types, re-org code and fix some issues

Merge pull request bytecodealliance#294 from no1wudi/main

2920fb4

Merge pull request #3 from wenyongh/test/riscv_aot

Implement mmap MAP_32BIT support for riscv

3dc93d2

Minor change of code comments

f3b7bee

Merge pull request #4 from wenyongh/test/riscv_aot

0a6ba90

Enable os_mmap with MAP_32BIT flag for riscv64

no1wudi force-pushed the main branch from ac977b7 to 0a6ba90 Compare July 22, 2021 02:03

wenyongh merged commit e4023c8 into bytecodealliance:main Jul 22, 2021

wenyongh referenced this pull request in wenyongh/wasm-micro-runtime Jul 22, 2021

Merge pull request #296 from bytecodealliance/main

1af82b7

Implement AOT support for RISCV (#649)

wenyongh mentioned this pull request Jul 22, 2021

[Feature request]: Support RISC-V backend #290

Closed

Implement AOT support for RISCV #649

Implement AOT support for RISCV #649

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