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martijnbastiaan
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@christiaanb How did you fix the |
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Drive-by comment: why not GHC 9.6? |
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I think the Cabal issue we saw earlier prevented us from upgrading one of the dependencies. |
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It was a cabal.project.freeze issue, in the original PR it disabled the pkgconfig flag for the zlib Haskell package; I simply put it back into the state it was previously: enabled. |
kleinreact
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| where | ||
| tmm = typeMismatch "Topology" v | ||
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| newtype FUN a = FUN (forall n . SNat n -> a) |
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That's an interesting new requirement. Also means we don't need ImpredicativeTypes any more.
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GHC was no longer happy with Maybe (forall n . SNat n -> a)
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@DigitalBrains1 I looked it up, it was indeed the GHC/Cabal issue:
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Thanks! That's a good thing to have documented here. |
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6fb0a795 Squashed 'clash-vexriscv/' changes from 2eced423..80b5dd9a
26856b58 Squashed 'clash-vexriscv/' changes from 0ac4a4f7..2eced423
88a7cf40 Squashed 'clash-vexriscv/' changes from 390818c9..0ac4a4f7
8e56cd19 Merge pull request #578 from bittide/lucas/smoltcp-hitl-test
0e954459 Add everything in `bittide-instances/data` to `data-files`
9b56e8f4 Add `vexRiscvTcpTest` to CI
5cbd1ed7 Add `VexRiscEthernet` Hitl test
7ffd46d0 add `ndisc6` to `shell.nix` to be able to use `tcpspray`
ef03ab45 Merge pull request #512 from bittide/add-smoltcp-example
3efa1b8a Fix `smoltcp` version to `0.11`
830c7654 axi::self_test readability refactor
0cb2c314 Small `axi` HAL refactor:
ae8c5013 smoltcp: Add `max_burst` configuration to Device
d8289f37 AxiRx: Raise buffer size to type level
a98dff8e AxiRx: Drop packets larger than our buffer
66a7ca4d Add MAC status printing to smoltcp_echo
d03016f4 Add MAC status interface to `vexRiscvTcpTest`
f8c692cc Add smoltcp example tcp server
fb28374a Add smoltcp Ethernet devices
16023631 Add `uDisplay` for `Duration`
b588adff Add `uDisplay` trait for `Instant`
1139d509 Remove unstable feature `panic_immediate_abort`
197e891c Add scripts for setting up hoeve (#620)
06507881 Switch from the 300MHz onboard sysclk to the 125MHz one (#643)
98c7997d Merge pull request #621 from bittide/lucas/make-wishbone-word-addressable
1879288e Make wishbone addressing word based
e1ba548a Merge pull request #642 from bittide/fincfdec-change-extra-clock-channel
bec1b072 FincFdec test: change the extra clock to use out1 instead of out0
27ed428c Correct the clock config name used by the FincFdec test
501c2ab9 Remove unused clock config `testConfig6_200_5_20`
ade6ba96 Fix duplicate Shake targets for CI (#641)
c9507c1f Merge pull request #536 from bittide/vivado-wrapper
8ce49786 Disable fourmolu for table
44bf0e43 Move HITL test control logic from Tcl to Haskell
06b3b088 Vivado-hs: support getting back return values
77f02b2f Add `vivado-hs`
1be068ee Make script for registering GHA runners more universal (#637)
dbba708e Fix and extend code comments (#636)
bc87829a CI: Allow tests to run even if linting fails (#635)
47ddc5ea Align value of `k_p` with Julia implementation of Callisto (#631)
4655a80d Merge pull request #633 from bittide/clock-config-500ppb
d08bd30e Add clock configuration for 500 ppb at 200 MHz
ee0b4223 Rename clock configuration project file to match other configurations
1d525a4d Merge pull request #629 from bittide/fix628
7fc3c914 Remove `Bittide.Link` (#626)
402f8e02 Add `LANG`/`LC_ALL` environment variables to CI
9b4fd190 Don't set DE mirror on CI
3c634970 Merge pull request #624 from bittide/cleanup-domains
653058f4 Remove unused domains
8d130c9c Remove unused `calistoSpi` instance
5a353aab Undo sorting of domains alphabetically
0c6cc472 Merge pull request #520 from bittide/temperature-monitor
4175bfe7 Add HITL test for temperatureMonitor
cb60601b Add temperature monitor function for raw ADC data
3a53328a Add SYSMONE1 blackbox and temperature monitor wrapper
101b7d17 Add label to Y-axis for buffer occupancy plots (#619)
78085eff Merge pull request #618 from bittide/remove-unit-juggling-fix-609
1cd1eca6 Directly compare expected and measured n.o. cycles
e1a2c093 Derive `Show` for `TestConfig`
4cabb412 Add `Bittide.Arithmetic.PartsPer`
fd3370ad Simplify `si539xSpi` instantation in `HwCcTopologies`
8adf4fef Merge pull request #617 from bittide/bump-ghc
dbaca88e Merge commit 'b24777a02ae829a490ff94d96ee2a8b8cb164c50' into bump-ghc
b24777a0 Squashed 'clash-vexriscv/' changes from 55ef807b..390818c9
0c0c1020 Bump to GHC 9.6.5
6a6ff816 Merge pull request #615 from bittide/remove-cc-simulation
e8f7a188 Remove clock control simulation path
d89be927 Remove empty test on CI
130fe730 Add `-Werror` for `bittide-{experiments,tools}` on CI
83968b3f Shift Y-axis according to clock offsets (#610)
d62ed314 Merge pull request #605 from bittide/clock-discrapencies-fix604
923297b2 Add regression test for #604
f68c6976 Flip sign of local fincFdec to fs conversion
e3e37567 Refactor to allow disabling clock offsets
38c01e1b Use `GthTx` as assumed domain diff domain
2bb79f66 Flip sign of `fsToPpm` output (#606)
f1bfb20f Merge pull request #602 from bittide/controversial-report-fixes
9968084b Use PPM as measure in clock plots
a03d0f7d Convert various units to `ms`
4d6893aa Merge pull request #601 from bittide/uncontroversial-report-fixes
5287e3c6 "end of simulation" => "end of run" to prevent confusion
80b4e383 Separate thousands with ',' in reports
39da209d Run `bittide-experiments:doctests` on CI
310587a2 Merge pull request #599 from bittide/no-fs
c887b5b6 Use `ms` instead of `fs` on x-axes
fc71ef20 Restructure plotting code for readability
94786b2c Merge pull request #596 from bittide/spdx-headers-first
0ad097ba Extend README with format instructions
763f8950 Extend git-blame-ignore-revs with SPDX header fixes
54ca5d2c Fix SPDX header formatting fallout
4e531464 Add `fix_spdx_header.py`
62d6d988 Merge pull request #595 from bittide/add-fourmolu
d49b63ef Ignore formatting commit for blame
a4e4b4b8 Format files using fourmolu
0a4f9798 Add fourmolu
1425ed3f Work around fourmolu parse error
f7bfc6c2 Merge pull request #594 from bittide/mvoe-hw-cc-topology-test-to-nightly
d1aefa64 Move `hwCcTopologyTest` to nightly
62c8cf37 Add missing `linkConfigurationTest` to nightly runs
6965c202 Merge pull request #511 from bittide/smoltcp-bitide-instance
b56b1580 Make separate jtag constraint files
e49623c1 Add `vexRiscEthernet` bittide instance
4a49db6a Make separate `sgmii.xdc`
4f95fe4f Add MAC status monitoring component
8d86e0df Add `Ethernet` `Mac` instantiation from `verilog-ethernet`
095e8e78 Add external hdl globbing to shake
e83f817c Bump clash version to include `gmiiSgmiiBridge`
661819ec Merge pull request #256 from bittide/add-wishbone-packet-buffers
2bb1e301 Large Axi4 refactor
ffc4d4ac Add documentation and tests
8cc8edd1 Clarify nomenclature, enable disabled tests
06d93cc9 Add Axi4Stream todo's
82d83a2a Add ILA for axi 4 stream
87f57b95 Add rust driver for axi interfaces + testing
b4c42ff3 Refactor axi components and add wishbone - axi interfaces
bad9de47 Add `leMult` haxiom
a617ea17 Merge pull request #573 from bittide/commit-year-ranges
8bea9ff0 Change copyrights to year of creation
9da07fa9 Remove `check_copyright_years.py`
dc3fe855 Merge pull request #505 from bittide/add-rust-logging
0caac67f Merge pull request #591 from bittide/lucas/bump-clash-2
79fd6598 Add formatting command to nix
a6b4c306 Add constraint-solver-iterations CI check
8abdf51e Constrain `constraint-solver-iterations` in `Tests.Axi4`
7b23be2f Bump all clash dependencies to current master HEAD
6378da1e Bump docker image GHC downgrade 9.4.8 -> 9.4.7
fa3a684a Downgrade GHC from 9.4.8 to 9.4.7
26e40ed1 Add `core::fmt` UART based logger for `log` package
467bfe1b Make `uart` not require mutability.
1631db02 remove unused rust-toolchain.toml files and panic handler feature flag (#588)
5db68a6d Don't hardcode IP addresses in CI scripts (#590)
2214ed36 Merge pull request #580 from bittide/better-ugn2
7d6cbfc4 Add ugn post processing
08c187a8 Calcute UGNs and check they are stable
7c67b2c5 Workaround bug in ghc-typelits-knownnat
9c2edb21 Simplify .gitignore
da2a78f4 Make nr of FPGAs more easily changeable per instance
19167eca Mark blackboxes OPAQUE instead of NOINLINE
36e1aaa2 Use proper domains for serial in/outputs of the GTH transceivers
0f4cbbe2 Rename DataCount -> RelDataCount
d3f37229 Merge pull request #577 from bittide/add-deviceIdentifierWb
fae81b7a Add `readDnaPortE2Wb`
361af6fe add `registerWbC`, Circuit version of `registerWb`
e81fb30c Merge pull request #583 from bittide/lucas/add-gild
512be010 Remove out-of-place comment
20d5607b Handle any hash digest length in `diff-clash-vexriscv-subtree.py`
909dce42 Squashed 'clash-vexriscv/' changes from cca33019..55ef807b
050d13fd Merge commit '909dce42e41e6478d86c1f72584256c87d4b935c' into lucas/add-gild
79081b8f Add cabal formatting check to CI
3139a970 make lint job use custom runner
3646516a bump docker image
3e1461c9 Format cabal files
6ac112b8 Add `cabal-gild.sh` formatting script
7039eb9f Add `pkgs.python311Packages.pyaml` to nix
bd8ab59e Add `haskellPackages.cabal-gild` to nix
fefe4068 Bump nixos to `24.05`
8ccec674 Add patches `verilog-ethernet` version (#579)
d46f927a Update register-runners.sh (#575)
6b56b8a2 Merge pull request #574 from bittide/random
ad0f7c70 Remove leftover `dom` from `wbToVec`
b2ef7621 Update `verilog-ethernet` nix hash
10001ae1 Check the link setup via data (#550)
2fec9694 Merge pull request #525 from bittide/add-user-data-to-transceivers
c4f8daa5 Inline `defTimeout`
9b9807a3 Deduplicate code by introducing `bitStep`
16af3f7b Add `transceiverPrbsWith` for more sensible API
82c00b8a Add word dealignment to tranceiver simulation tests
b0446b66 Add more debug probes to transceivers
6454c325 Add test cases for PRBS and fix errornous assumptions
411a56c6 Add basic simulation tests for transceiver logic
afd8a339 Factor out GTH core as argument to `transceiverPrbs`
9fb71469 Use makeTopEntity again
4e8a5dd4 Overhaul transceiver functions to allow for user data
0659bc1c Apply HLint hint to remove parentheses
02c8b2d0 Do not respond combinatorially to input in `prbsChecker`
fcfb777c Make PRBS config polymorphic in width, add documentation
041b0449 Move PRBS functions to own module
f00dd10a Split comma and PRBS generation
703b881e Bump `clash-protocols` (#533)
14c1c8cc Merge pull request #531 from bittide/shorter-ila-name
e09d436d Correct hourglass argument order (#532)
5753ae2b Use module name as short name instead of ILA name
c5de1412 Add explicit module name for `ilaWb` wrapper
92665fd1 Use `setName` to explicitly name ILAs
1e34883e Fix ILA short name
33c4135f Fix hourglass topology
b7c8f228 Add more topology types (#526)
4132f442 Add `rusty-callisto` flag to Cabal (#527)
b8689b5b Work around empty pattern error on CI (#524)
fc23913a Pull post synthesis build products from local cache (#522)
ba00523a Use record for transceiver output(s) (#517)
fc4cfd5f Merge pull request #516 from bittide/various-simplifications
07e50787 Simplify type signatures of PRBS functions
1fe98719 Remove (irrelevant?) inversion code from PBRS functions
55fe5677 Consistently name test groups
6c35d233 Remove kernel bug workarounds
e387d22d Align exported EB data with the selected topology (#515)
a8b028ef Re-enable reframing for simulation (#514)
2bdea6e7 Add more parameters to the HITL topology test (#510)
29bb7941 Improve the clock reports (#509)
730e33c5 Merge pull request #508 from bittide/fix-tcl-typo
b43a2b3e Fix tcl typo
9c11c27e Merge pull request #482 from bittide/elf-mem-padding
82a6c602 Add `CargoBuildType` to discriminate between debug and release builds.
e5c87c2a Allow padding of initialized ELF memories
d98c73e8 Add missing HITL test to staging (#507)
6efac7c2 Remove remaining references to removed MVPs (#506)
a6f0e65d Add HITL topology test (#471)
f0504a7c Merge pull request #504 from bittide/move-to-nightly
b6f3c41c Move overlapping tests to nightly, remove obsolete MVPs
3d76c1e2 Merge pull request #492 from bittide/switch-to-Nppm
652f08c8 Switch to a step size of 10ppb
23b94d06 Add 10ppb, 100ppb, 1ppm clock configurations
eeae0d9d Add step size to Si5395J config
d41c705a Merge pull request #424 from bittide/add-jtag-martijn
a48d4155 Add input registers to ILAs
16b0709c Add JTAG to processing elements
f1cd8c81 Use 80/100 in VSCode
471b34e5 Squashed 'clash-vexriscv/' changes from 8c7f90a..cca3301
f51874b1 Merge commit '471b34e5e5719e64a0b03edba56342e4e5b06645' into add-jtag-martijn
4f1d789f Embed plot generation into the tools (#503)
7eeb9e95 Use upstreamed version of `DNA_PORTE2` (#501)
8e39ff08 Merge pull request #500 from bittide/ghc94-upgrade
4bff0e34 Nat.Extra constraint have correct shape
4d74d8b9 Upgrade to GHC 9.4.8
99290510 Refactor simulation, plot & topologies (#499)
0a529b50 Add link configuration + tests (#495)
99482c53 Support online artifacts for plotting (#494)
9544202b Merge pull request #498 from bittide/add-disabled-jtag
6a35568a Tie off JTAG signals
5b814ff0 Add `scripts/diff-clash-vexriscv-subtree.py`
8444eb61 Move `update-clash-vexriscv-subtree.sh` to `scripts/`
c533a386 Merge commit '995ab1653749d2d911e7c768d31f3998b68da86d' into add-disabled-jtag
995ab165 Squashed 'clash-vexriscv/' changes from 6a0805f..8c7f90a
15897d52 Run Docker in priviliged mode with host mappings on HITL runner (#497)
1ff34562 Merge pull request #486 from bittide/parse-clock-control-registers
45ade506 Enable multiple threads when compiling sources (#493)
0e648942 Simplify implementation of `parseHex` once more
2793eabd Merge pull request #491 from bittide/error-unmapped-addrs
fb152d5f Support postproc data in HITLT configs (#490)
eb9e6179 Add comments to `parseHex`, add tests
00d78bfd Simplify `parseHex` by using `{from,to}Integer`
b4f21b77 Parse Si5395J registers from CSV
4fce37d4 Use patched version of Hedgehog for better error messages
008a7e0c Error for unmapped addresses in `singleMasterInterconnect`
15dd4d73 Rename `MemoryBus` to more descriptive `MemoryBusAddrWidth`
f7c25753 Add generated CSVs to artifacts (#489)
5e020659 Output post processed plot data (#488)
b2516612 Make `linkStateTracker` more strict (#485)
07032e2c Loosen memory address restrictions in `MemoryMap` (#484)
cadbe9d1 Fix shake dependencies (#483)
6f53c7cc Reduce simulated topologies to the safe ones (#480)
8e70f595 Don't run copyright check at night (#479)
73275bca Bump `clash-protocols` (#478)
9d20cb60 Make building OpenOCD deterministic (#477)
51aa8488 Project Structure Update (#469)
073c5ef1 Merge pull request #474 from bittide/bump-nixos-23.11
022a6549 Fix bug where VIO values are not printed in Hitl tests (#475)
ce7bcb57 Merge commit 'b06e3843e2985aa313116707de5506882174e24e' into bump-nixos-23.11
b06e3843 Squashed 'clash-vexriscv/' changes from e21bc16..6a0805f
0f99244e Bump to latest local dependencies
900a19b1 Ignore `clash-vexriscv/` in `check_copyright_years.py`
97e0d290 Add `update-clash-vexriscv-subtree.sh`
b69bc0bd Bump to NixOS 23.11
f1912fb7 Remove useless 'buildPackges' form 'shell.nix'
9d0987d5 Use proofs instead of tests (#470)
93e7d6e0 Merge pull request #462 from bittide/add-hitlVio
8358c519 Merge pull request #457 from bittide/vio-yaml-infra
198f9f73 Add `hitlVio` and make tests generate their own test data
33ca9d66 Add documentation to `HardwareTest.tcl`
95028833 Rename 'default' to 'defaults'
98b2a091 Retry reaching `cache.nixos.org` for 5 minutes
82325c69 Cleanup of `HardwareTest.tcl`
0c211a03 Replace all `puts` + `exit 1` with `error`
dbae4306 Add `extraProbesTest` to HITL
53cfa67f Add yaml based vio configuration.
1f29d772 Add copying of `vio_config.yml` for `bittide-instances`.
fc5f4a07 generalize `getConstraintFilePath` into `getInstanceDataFileName`
5d243e30 Fix erroneously formatted comment causing Haddock to fail (#464)
0c2fcdf1 Use `--locked` flag when calling `cargo install` (#465)
c55659eb Merge pull request #400 from bittide/add-timer-wb
3b30cda5 Add a wishbone accessible timing utility.
cce78db9 Run `cargo fetch` before running a `build --frozen`
b9c297c6 add `rust-toolchain.toml`s to `CARGO_KEY_PATTERNS`
53d90928 Merge pull request #252 from bittide/add-DeviceId
66332875 Add device ID extraction
964ce763 Also check Cabal copyright notices
d970db11 Merge pull request #463 from bittide/copyright-fixes
f6b0cca0 Return 'False' if commit doesn't have a valid copyright notice
4e2e93b8 Don't error if changed file does not contain copyright notice
ae0e2690 Don't execute check_copyright_years.py on nightly
038b7171 Print extra debug information on unexpected errors in check copyright script
1e71c470 Add `license-year` check to CI (#461)
1c0f177c Switch SYNC_IN/OUT cable setup (#458)
c02ba287 Merge pull request #459 from bittide/ci-updates
2eb9e3c0 Upgrade actions for checkout and upload- and download-artifact
888781f1 Add maximum memory usage for docker containers
eeb354ca Fix asymmetric buffer occupancies (#453)
530e2b98 Move clock control to the stable clock (#452)
5aa4b8ec Fix Ext200A/B reset kind (#448)
93a785b1 Fix and improve ILA plots (#415)
649a432c Require `Cargo.lock` and cache to be up to date on CI (#447)
650f1468 Print hex digests of individual files in `cache.py` (#446)
530a3a7d Clash 1.9 update (#444)
735f33c4 Merge pull request #445 from bittide/increase-wait-time
2ac8d777 Increase wait time
0f26e6bc Merge pull request #442 from bittide/move-bittide-build-server
d5c920fb Move bittide cache server to local machine
a69aa998 Update docker images
43a1af27 Update bittide build server scripts
18818837 Merge pull request #441 from bittide/jtag-prep
aec83a7b Make `ilaWb` configurable in stages and depth
1e274c87 Add forked version of OpenOCD to Nix
1f2374c6 Simplify VIO logic in `Bittide.Instances.Hitl.VexRiscv`
ea0de34c Allow targets to set additional XDC files
d7cae0b4 Use `-notrace` when calling Vivado
61775f7a Use `-notrace` instead of `-quiet` in TCL
e48f4e18 Add `capture` and `trigger` ports to `ilaWb`
b100ab8a Merge pull request #440 from bittide/update-vexrisc-subtree
c7026346 Squashed 'clash-vexriscv/' changes from 2b08a77f..e21bc165
df95db6b Merge commit 'c7026346838ce072449b58ce61bd80807b33018c' into update-vexrisc-subtree
85744c8b Merge pull request #417 from bittide/fix-simulation-plots
1598d886 Fix stability indication mask
8497c20b Merge pull request #433 from bittide/fix-synth-nightlies
322365ef Clean up module `FullMeshHwCc`
691d7b6c Clean up module `FulLMeshSwCc`
498a72c8 Add documentation for selective CI synthesis (#426)
d631a75e Use `!cancelled()` instead of `always()` (#432)
93b607b9 use `Result` for finding `program-stream` executable for better error messages (#428)
667c3547 Merge pull request #420 from bittide/ila-post
c667d498 Merge pull request #421 from bittide/dependabot/cargo/firmware-support/rustix-0.37.25
ff6c0197 Add post processing step to HITL infrastructure
aa16b201 Switch to local caching on CI
0eeb8734 Increase memory size for firmware binaries
921d9b64 Add double quotes around parameters in bash scripts
dbb074df Write out vivado exit code for caching purposes
5c716f21 Restructure bittide-instances
ed0c405e Add ILA to boardTestExtended
b1ca4d15 Rename 2 BoardTest instances with long names
f8011968 Add local cache script
c6f2f5c4 Merge pull request #427 from bittide/minor-rust-fixes
4916614c Produce Rust binaries in `_build`
9b348390 Use `-v0` when executing `list-bin` in `program_stream`
3b29c0e9 Remove outdated comment
ab97a1f5 Don't reset start_probe after HITL test finished (#423)
b4c6a5e9 Merge pull request #422 from bittide/ci-selective-synth
12758ca2 Remove unneeded restore-keys and cabal freeze from CI
34186508 Add selective synth and test CI runs for debugging
abb4eab7 Bump rustix from 0.37.19 to 0.37.25 in /firmware-support
3b2ad485 Merge pull request #403 from bittide/clock-control-firmware
a7e9f034 add full mesh software clock control instance
90b9579f add clock control binary, remove fdt-read example, no default panic handler
e90da4ab Add memory mapped clock control
a0e4f271 Add `+RTS -xp -RTS` to `clash-vexriscv-sim` (#407)
a0f122a1 Merge pull request #406 from bittide/fix-test-reset
b34199b2 Fix FullMeshHwCc resets
1338fd3d Merge pull request #399 from bittide/ila-based-plots
0afb33c0 Add HITL Plot generation to CI
167a71c0 Add postproc plotting
b80c3c41 Add ILA for dumping plot data
859f754e Remove ill-advised options from GHA runner system config (#405)
74571e5f Increase stability checker margin
89ba916a Set trigger position to 0
f23b4e80 Merge pull request #401 from bittide/cc-debug
0119d906 Wait longer for stable, disable reframing
13e4586c Use `cabal.project` in cache key calculation (#404)
319766b0 Add FINC/FDEC monitoring
0fbeba4f Add 'Clash.Cores.Xilinx.Xpm.Cdc.Handshake.Extra'
c81b9625 Shorten CI names to accomodate GitHub UI
a2c3331c Use 1ppb steps in `testConfig6_200_on_0a`
d0f2a069 Fail `FullMeshHwCc` if transceivers go down during CC
a502649f Only consider transceivers stable if they stay up for 50 seconds
0fa2e5d6 Rewrite shorten names logic in Python for CI
84011fda Merge pull request #292 from bittide/add-processingElement-instance
065994a3 remove `bittide-instances` dependency from `get-data-file-name`
3d711239 Add working processingElement instance with uart
d8b5adb9 Merge pull request #361 from bittide/callisto-rust-ffi
45577cfd Integrate Rust FFI into bittide
11d46346 Separate interfaces and reorganize Callisto crates
a11b29fd Add Haskell/Rust FFI interface for Callisto
10ecc666 Merge pull request #398 from bittide/short-ila-probe-names
e94aa566 Use short names in VCDs/CSVs generated by ILAs
30e3ceb2 Apply `-xp -xm20000000` to doctests
d229d1a2 Consistently apply GHC options to all executables
677576f1 Add instructions to locally reproduce error to error message
3a3e5db3 Use intermediate `watch_files.txt` to invalidate caches
142b0c90 Bump `doctest-parallel`, fix its invocation in `bittide-shake`
97d78df9 Add `cabal.project.freeze` and lock the `index-state`
3b7fa67e Merge pull request #397 from bittide/fix-nightlies-2-electric-boogaloo
eb7f857b Memory allocation bug hotfix (#396)
f3bc9e86 Only use one clock for `counterReducedPins`
3070f4b2 Add `shake` as command alias in Nix shell
1185833f Merge pull request #395 from bittide/various-fixes
aac9412e Publish ILA data on CI
4083d9fe Timeout per test instead of per test per device
48bd6ec6 Remove false dependencies and empty modules
d27bc12a Clean Cabal cache before calling it
f4791b15 Simplify calling cargo in Shake
f02ed681 Account for deleted files in `get_watch_files.py`
d8a1c394 Add `Clash.Functor.Extra`
24ba5d3d Fix copy+paste error: goTransceiversUpTest => goFullMeshHwCcTest
733f20b7 Fix bug where hardware test with ILA could fail without error message (#394)
b0be4850 Repair `clockControlDemo1` nightly (#393)
613bb1e5 Merge pull request #392 from bittide/simplify-tranceiver-logic
80e0e238 Simplify tranceiver API: only expose general reset
d110e98d Use 'done' signals as clock locks
2b020d51 Add support for ILAs in hardware-in-the-loop tests (#389)
329dbcb4 Add `fullMeshHwCcTest` (#308)
6e8199e2 Merge pull request #387 from bittide/various-tcl-improvements
a86b668d Fix bug with for multiple VIOs in hardware-in-the-loop tests
dc1a23da Improve clearity of stdout during hitl-tests
0def42ee Set name of vioProbe components
a6992996 Move `BoardTest` to `Tests`
218f263c Merge pull request #386 from bittide/add-transceivers-hitl-test
e65b5c99 Add `--init` to docker options for Vivado synthesis
f6955862 Restructure and document reset infrastructure
7009ef4d Add `SYNC_IN`/`SYNC_OUT`
94716e09 Add `transceiversUpTest`
bf010255 Reduce timeouts in `gthResetManager`
d01b61d2 Reset transmitter if receive doesn't find a stable link in 10 tries
691b5916 Resolve CDC issues in `Bittide.Transceiver`
46a0fcab Expose `Clash.Cores.Xilinx.GTH`
1371bf86 Use `DiffClock` in `ibufds_gte3`
12f5674d Add `BitPack StabilityIndication`
8b1aeb29 Revert change of updated FPGA id in demo rig (#388)
88ee80e3 Merge pull request #362 from bittide/add-cargo-support-to-shake
412b90b5 Remove `cabal.project.{formal,simulation}` in favor of a single file (#384)
116b9160 Add `Clash.Explicit.Reset.Extra`: reset convenience functions (#383)
e8ca7156 CI now builds `firmware-binaries` and creates an artifact All jobs that require the `firmware-binaries` can download the `cargo-binaries` artifact.
00ad2068 Add cargo building to shake targets
62b9294f Add `testConfig6_200_on_0a` (#382)
7199dd2d Add `storedByte` to SiSPI driver's state (#381)
18fdcccf Remove auto clock group code (#379)
6b38dd33 Merge pull request #377 from bittide/f-extension
4ec2ca9f Squash place, route, and netlist generation into one command (#380)
83a3d3c2 Bump Clash for reset related convenience functions (#378)
a9205213 enable F-extension in firmware-binaries
9e881289 Squashed 'clash-vexriscv/' changes from 093f08f..2b08a77
ba5bca05 Merge commit '9e8812892a098babed35f066e328145d787a1dd5' into f-extension
5ede31e3 Add HITL test for `SYNC_IN`/`SYNC_OUT` hardware (#375)
d4a436b3 Merge pull request #363 from bittide/firmware-reorganisation
4d6962cd fix clippy warnings
51f7ad2a reorganise Rust crates
abdb6d33 Update FPGA id of replaced FPGA in demo rig (#376)
4210e64c build `get-data-file-name` before running it (#374)
cefc01c3 Add `processingElement` hardware-in-the-loop test (#371)
249bcefa use `clashCompileError` in blockram components. (#373)
41771475 Correct a typo in nixpkgs.nix (#370)
c2e67cf1 Ignore module names in probe names for HITL-tests (#367)
3ec2b90b Merge pull request #368 from bittide/fix-need-xdc
a0ce85d6 Remove duplicate test which excluded `targets`
0268f656 Only search for constraint file when needed
68b6a89b Don't cache Shake's `_build` on CI (#364)
9570b684 Separate `bittide-instances` into `bittide-instances` and `bittide-shake`(#360)
bd9c7e89 Merge pull request #316 from bittide/fincfdectest
e62f6693 Add FINC/FDEC test
ff7dc6a6 Increase hardware test timeout to 60 seconds
1f8562e7 Add 'testConfig6_200_on_0a_and_0'
8a2065ba Bump Clash, remove obsolete `KnownNat (DomainPeriod dom)` (#359)
aa18c7a6 Bump Clash, use new naming convention (#358)
c19588d2 Merge pull request #357 from bittide/bump-clash-diffclock
503b3da0 Revert "Remove create_clock statements on negative clocks in Clash generated SDC"
c31bfff4 Bump Clash and use `DiffClock`
8a20d459 Merge pull request #355 from bittide/simultaneous-hw-tests
6725c536 Run hardware tests in parallel
07498595 Merge pull request #284 from bittide/clash-protocols-processingElement
0ec3ec64 rewrite `processingElement` as `Circuit`
ac29994f Add circuit wrapper for wbStorageDP
26ae1ea1 Adjust `singleMasterInterconnect` type
716ae6b2 Add synthesis cache on CI (#351)
8dc000bf Add Axi4 scaling components (#255)
906ed633 Merge pull request #347 from bittide/add-drc
8002383a Remove create_clock statements on negative clocks in Clash generated SDC
90b8faba Add design rule checking to Shake
49b9f42c Merge pull request #348 from bittide/optimize-artifact
0c6693cb Decrease artifact download size for hardware tests
7ad875fd Exclude TCL scripts from Clash cache invalidation
a4fac244 Add `extendedHardwareInTheLoopTest:test` to nightly
b96bb4c3 Specify individual hardware targets with Shake (#332)
c56e0683 Retry connection when HW server has too few targets (#336)
cd7f2a50 Make all bitstreams compressed (#340)
f6292368 Add `.envrc` (#330)
548627cb Run CI earlier at night (#337)
f1984af6 Merge pull request #335 from bittide/fix-334
48a426f1 Add error when no start probes are found in hardware test
c3d50652 Change indentation of Tcl to 4 spaces to match `clashConnector`
c7eb9fb2 Fix synthesis for instances without IP (#333)
8092f0a9 Add systemd service file for Vivado Hardware Server (#327)
87702a10 Merge pull request #331 from bittide/fix-legend-positioning
50e326bf Improve legend positioning
92747492 Merge pull request #322 from bittide/sim-startup-offsets
d02c6325 Add GTH primitives and PRBS link checking code (#306)
41badc40 Add support board specific IP generation (#325)
22efc94a Add legend to report
eb1ccc72 Add initial startup offsets to simulation
b40557aa Move Vivado dependencies from runtime to docker image (#323)
03735574 Allow multiple hardware tests on one FPGA (#321)
eac993ea Merge pull request #320 from bittide/less-pessimistic-cache-invalidation
792a9190 Encode crypto hashes of needed files in TCL scripts
7d701258 Use source files instead of dist-newstyle for cache invalidation
49884017 Add note to brittle 'need' construct
0ede0d0b Correct spelling mistakes
bcfa0a80 Add 'bitstream' and 'Vivado' to known words in VSCode
302feac2 Add Python temporary files to .gitignore
f59cbaf4 Remove unused false path hack (#319)
556ce09d Merge pull request #318 from bittide/probe-print-on-fail
9f57a942 Print all VIO probes when a hardware test fails
c379bb38 Clean up timestamp logic in `HardwareTest.tcl`
f742309c Repair timeout logic in `HardwareTest.tcl`
b65bdb4d Fix bug where an unfinished hardware test could be successful
66446202 Add hardware in the loop testing to Shake (#309)
478f300a Run Bash in safe mode by default on CI (#313)
e64c56eb Use relative files in Shake, but set CWD to project root (#314)
b46ea6c6 Merge pull request #312 from bittide/safe-ci
26694080 Run all-check in lint step
5ba8c4df Check whether all self-hosted jobs run in a docker image
911c46ae Remove formal test tools from nix.shell
4a786b02 Update Docker images to contain latest Nix additions (#311)
c814d869 Use well-formed dictionaries in haxioms (#297)
6827257f Use `compute` label in addition to `self-hosted` label on CI (#310)
f51d36a0 Merge pull request #279 from bittide/callisto-update
dec8bcb7 Add 'detect, store and wait' reframing approach
e4daf698 Add flag to Callisto to make reframing optional
89f68ec7 Test detect-wait-reframe approach
aee4c2c4 Export stability and being-settled indication
e4f4a88c Switch elastic buffer to bittide counter
d6a76cbd Switch 'DataCount' to 'Signed'
04f6fadd Stability check based reframing
17c7d989 Callisto Algo Update
bb0e2706 Merge pull request #295 from bittide/simulation-report
409e19a7 Simulation report generation
a8cf63ed Merge pull request #300 from bittide/streaming-program-format
d67f6a0f Add `uartIO` for simulating UART circuits. (#276)
f5be39fe Merge pull request #305 from bittide/missing-uartWb-doc
a1b41f1c Add missing Haddock comment to `uartWb`.
316fd91c Add memory mapped `uartWb` (#274)
e96f7e10 Simplify wishbone storages (#277)
2a660a7e add ProgramStream binary, add tests for program streaming
814e770e use a custom program streaming format
bb866494 Merge pull request #298 from bittide/firmware-elf-size
fda19adf use separate Cargo workspaces
4860a38b use different Nix Rust overlay
c7b181a6 Add ELF/DTC interpretation utilities (#246)
ffa6fa88 Add `Bittide.Extra.Maybe` #294
a64447d4 use `elf-limits` on firmware examples in CI
440f19fe use ufmt for firmware
c981ea2c Add `bittide-extra:doctests` to ci
93f2bca0 Add `Bittide.Extra.Maybe` use cases
2926c498 Add `Bittide.Extra.Maybe`
4b69b043 Add `-force` to `write_bitstream` in Shake (#293)
9a4f5c8e Add `Bittide.Counter` (#289)
23b31d43 use nightly and optimise stdlib
221e8b73 Merge pull request #281 from bittide/change-contranomy-to-vexriscv
53a53673 update licenses for new subtree
03c4facb Squashed 'clash-vexriscv/' content from commit 093f08f
7d9a2443 Merge commit '03c4facbcbe8862dd6ace2cc9b33539136f8b8a9' as 'clash-vexriscv'
0d5d1c85 remove contranomy
4cd6f095 remove vex-riscv package, use clash-vexriscv
d0165b6e Merge pull request #278 from bittide/shake-flash
0f448110 Add board programming to Shake
a25fc7a7 Merge pull request #272 from bittide/bitstream-gen
17bc2d17 Add bitstream generation to Shake
8131a1c7 Make clock control demos standalone
587d05b3 Add differential input buffer primitive
45111caf Upgrade Clash for updated Xilinx clock wizard
96cd24c2 Merge pull request #251 from bittide/double-ack-test
2b56d199 Merge pull request #265 from bittide/json-syntax-fix
12f833fa Fix JSON parse error
ea123489 Merge pull request #264 from bittide/stability-check
f11ae9c4 Write settings before simulating
e25d4285 Disable formal checks on CI (#263)
cb3fa862 Add doctests to `bittide-extra` (#262)
503dec28 Fix simulation time and memory requirements (#260)
bd4407d0 Remove obsolete comment from `fromListWithResetAndEnable` (#258)
261e3f9e Remove `wishboneSink`s from `processingElement` (#254)
7f49281c Merge pull request #259 from bittide/stability-check
a1a72ce1 Add test using clash-protocols to wbStorage to check for double-ACKs
fb38ae04 Fixes divide-by-zero and exhausted heap
f0ed1d38 Add `spiFrequencyController` (#216)
13c026bd Add `verilog-ethernet.nix` (#257)
adc5a301 Add `fromListWithResetAndEnable` (#253)
f2636f54 Update Si539x configuration component (#215)
cb920b8f Make (union dMem fdt) error on overlapping elements (#250)
c0d45b7c Merge pull request #245 from bittide/stability-check
94939d7f Added stability checker to the simulation
4f1e28bf Fix typo in `README.md` (#248)
60ee75eb Merge pull request #247 from bittide/staging-main
ca06b7c9 Run formal tests on self-hosted runners
b4d74752 Only run expensive CI during nightlies and on 'staging'
4e8dc636 Replace `git` call with `../..` logic
7feb50f0 Merge pull request #227 from bittide/nix-shell
826d8211 Update GitHub Actions actions to prevent warnings
3f4a513d Update README.md to indicate we use Nix
c7bc1e7d Don't accidentally override caches in post-build jobs
a6b2e384 Add Nix to CI
6afe928d Remove genplots.py
69794d17 Add `shell.nix`
f2b84d2f Merge pull request #244 from bittide/vex-riscv-tests-no-binaries-error
a4d63831 Apply clippy suggestions
df500025 Make VexRiscv integration tests error when binaries are missing
6e4c9f2b Update Rust version
b44dac8e Bump elf_rs from 0.2.0 to 0.3.0 (#240)
0a85000e Merge pull request #198 from bittide/VexRiscv-integration
add92b53 add vex-riscv package
ca700a28 Merge pull request #237 from bittide/typelits-version-constraints
75390c77 Added typelits package constraints
10dc72de Merge pull request #235 from bittide/more-ci-changes
8e3c1e20 Move non-Vivado jobs back to public runners
a4aae0dd Revert "Use 'de.archive.ubuntu.com'"
6162061c Run CI on every push and branch (#234)
91e9a9c0 Merge pull request #226 from bittide/runtime-topology-update
82b4e756 Remove use of TH for graph composition
ba09e4ae Use type level `Nat`s in `Graph`
cd57f097 Add link availability mask to Callisto
caaa24e9 Commit Cargo.lock file for the workspace (#233)
0e0d5064 Merge pull request #232 from bittide/riscv-dep-update
c0cc2201 update riscv-rt and riscv crate dependencies
d9123b8d Add Clock control demo1 to bittide-instances (#195)
a587e1b4 Fix Rust warnings in CI (#230)
3bb26228 Merge pull request #229 from bittide/bump-ci-actions
6e97ce2f Add cachebust to cache keys and update clash container image
53b1b5dc Use `actions/cache@v3` on CI
22977c5a Use `actions/checkout@v3` on CI
d5aa41a3 Use 'de.archive.ubuntu.com'
4cb70f1f Add missing shake instances to CI (#222)
a0cbc40f Add `scatterUnitWb` and `gatherUnitWb` instances (#220)
1a5a1ddc Expose read/write data ports of elastic buffer (#214)
24bafaa2 Refactor singleMasterInterconnect (#155)
b92ba9bc Work around clash-compiler#2376 (#213)
e782d9c3 Remove redundant bitCoerce from gatherUnit (#218)
0ece4848 Improve endianness throughout designs + rxUnit refactor. (#158)
70065267 Merge pull request #153 from bittide/wbStorage-bugfixes
ad46b254 Cosmetic changes in wbStorage'
0933d342 Fix addressing bug and change test to cover bug
93bb21d4 Add clock control demo 0 to `bittide-instances` (#192)
2429329f Add `doctests` to `bittide` (#212)
7e9127d3 Add clock configuration core for Si539x chips (#199)
1a585343 Add type level time units (#201)
f1eb9ef4 Merge pull request #210 from bittide/dffsync
26077cff Add more temporary Vivado files to .gitignore
daea21c6 `safeDffSynchronizer` with SDC files
eedb0ce0 Merge pull request #211 from bittide/check-deps-in-all
0d7f6d35 Check dependencies for failures on CI
bfa6d4b5 Fix fallout from #190
20f3264a Lower number of Hedgehog tests in `bittide` (#202)
d0a609a6 Add elastic buffer stability checker (#190)
ebf42c09 Add a controlled version of `xilinxElasticBuffer` (#189)
9811540f Add Tcl to place all clocks in asynchronous groups (#197)
ef84986b Add Xilinx specific 'tripleFlipFlopSynchronizer' (#191)
d13776e6 Merge pull request #188 from bittide/only-run-formal-on-main
05551594 Add `cabal.project` to has_riscv_changes.sh
f0280f5e Only run RISC formal tests on 'main'
2d034d27 Merge pull request #186 from bittide/add-callisto-instance
ef691275 Add 'callisto3' instance
7254fc28 Add 'all' target to shake
489837c0 Add FileVec as target for wbStorage' (#185)
4a923898 Merge pull request #177 from bittide/simplify-hierarchy
cab9f1ec Move callisto to 'bittide'
d0ae004a Move 'elasticBuffer' to its own module
b238a46e Simplify `Bittide.ClockControl` hierarchy
ea3bface allow component-wise initialisation in firmware (#140)
87526bec Correct timing constraint failure check (#182)
5db8e803 Pad calendar's initial contents with defined values (#180)
66a1e49c Use absolute build dirs in Shake files (#183)
dfd1d417 Remove strict unbox optimizations (#179)
d53cd26c Use femtoseconds instead of picoseconds (#175)
26538783 Merge pull request #184 from bittide/add-all-check
75dd62ae Make sure 'all' lists all tests
096fb758 Work around invalid Cabal parsing logic
24fc8119 Merge pull request #181 from bittide/fix-memleak-elastic-buffer-sim
52058ad5 elastic-buffer-sim CI: test plot code for memory leaks
cf57d3a2 CI: update set-output to new syntax
f79c93d0 elastic-buffer-sim CI: remove dump csv -> plot csv test
c29255c0 Fix memory leak in elastic-buffer-sim
fc91055a Add ip component specific vivado subdirectory (#178)
e4965a45 Use type level nat in `DataCount` (#174)
cd79d067 Use `clockTicks` in `elasticBuffer` (#172)
34f41b1b Fixup main (#176)
1fc42abb Merge pull request #118 from bittide/compressed-calendar-support
d2207f83 Add node implementation (#103)
4849b958 Scatter / Gather stalling address (#122)
c08bb850 Add compressed calendar support
2385f026 Add gppe and managementUnit (#105)
8f68f84f Use `MemBlob` for initial contents in `wbStorage` (#148)
ef86c500 Add axiom `euclid3` (#171)
07a00e70 Add property tests and documentation for haxioms (#170)
8f588462 Merge pull request #166 from bittide/update-rust-riscv-rt
7d1c7bd3 fix firmware programs building on Rust 1.65.0
4b57c30b Add wishbone sink and character printing function. (#154)
9d9c2b48 Merge pull request #159 from bittide/synthesizable-callisto
d93fb9f8 Use Xilinx IP in `callisto`
194bf76d Refactored out mealy from 'callisto'
5e1f3c53 Use hidden clocks
ce268986 Calculate `r_k` using `Unsigned` instead of `Float`
b10b3638 Remove ClockControlConfig argument from 'callisto'
485b8d0a Add instances: `ToField (Unsigned n)`, `ToJSON (Unsigned n)`
ac51e5bc Add complete2 as a plot option
a24906c3 Elaborate name: sgn => sign
2329b5ff Don't warn about post import qualified
15462e00 Use updated TCL API and run synthesis on CI (#163)
3f5e0c50 Add 'bittide-instances' and synthesis build system (#112)
3b82ef22 Update to latest Clash and add `clash-cores` (#160)
fc5d3f41 add scatter gather configs (#104)
52ef0bf8 Add Done state to rxUnit (#149)
d3035f59 use mealy machine (no destructuring signals) (#142)
dc46d6a3 GPPE implementation (#66)
bd395b87 Switch remove reorder buffers and add rxUnits + txUnits (#71)
f2825a91 Initial instruction memory element (#32)
22956e22 Exclude riscv-formal files from language stats (#147)
3d168ab9 Merge pull request #145 from bittide/run-on-self-hosted
5b47e30a Run formal checks on public runners
9e645f08 Add register_runners.sh
fe7d0499 Run Hedgehog tests with 1 thread
a4b6ca38 Run CI on self-hosted runners
34eb7602 Merge pull request #127 from bittide/firmware-metacycle-register
ee7f07bf Merge pull request #138 from google-research/strip-binaries
0c92b191 Cargo: Strip symbols and optimize for size
27fd2466 use Float over Double (#130)
b906ffa2 add firmware abstraction for metacycle register
fe9beb76 Add some topologies to the CLI (#133)
0e2548ed Clean up codebase (#134)
4437dc1c use clash-protocols for Wishbone types (#113)
00d078d8 add hypercube, line graphs (#128)
cd7a704f Implement new clock control algorithm (#119)
20d949cd Test infrastructure: HUnit for contranomy, firmware integration tests (#38)
4657d306 Plot clock periods and elastic buffer occupancy using matplotlib (#111)
6fc52e68 Mention reason for disabling HLint hint in Wishbone.hs (#117)
7cc62ec4 add 3d torus (#114)
0ec8894c Add a 2-d torus to Bittide.Topology.Graph (#110)
df8de14b Add simple topologies; observe system behavior by dumping to csv (#88)
268db8f3 Comply with dynamic clocks API (#107)
be2b4092 Fix failing memory-map test (#102)
f33f1a36 change rxUnit API to match txUnit (#101)
7bf33bcc Controlled calendar switching (#73)
d3e61f5e Add NOINLINES to reduce HDL file sizes and help synthesis tools. (#100)
4c07f09a Merge pull request #98 from google-research/bound-clock
549ab80c Bound frequencies; will not request outside its range
7e3428c1 Fix tunableClockGen (settleCounter incremented inconsistently)
7bbca024 fix slownDown -> slownDown
37e99b14 Merge pull request #87 from google-research/add-elastic-buffer-sim
fe6f8cfc Add 'elastic-buffer-sim' to CI
98974c28 Add elastic-buffer-sim
67055dfd Force HLS version to 1.6.1.0 (#93)
28850c54 Timing oracle hardware support (#69)
8a533377 Move wishbone to Bittide.Extra (#72)
7584bc79 Change double buffered memories (#86)
7bd4b970 Initial implementation for the memory map component (#33)
78f1f8b2 Renames calendarWB to calendar. (removes old calendar) (#85)
fd49f4a1 Add -Werror contranomy-sim in CI. (#89)
e844c438 Add firmware support for gather and scatter units, device tree loading (#67)
6d56591b Small fixes (#83)
4789f33d Add -Werror to CI for bittide (#84)
0687ff79 CI: fix retest logic riscv-formal tests (#81)
ea16cabc Implemented scatterUnitWB and gatherUnitWB (#31)
7d78cda2 Remove old DoubleBufferedRAM file
6cc27717 add linuwial haddock styling
12a0d498 Enable multithreading for unittests
ec9aae7a Applied acronym naming convention.
0cdf3ca8 Adjust S/G units to use uninitialised memories
28b5c8b7 Add uninitialized versions of memory components.
5d7df0c6 Initial registerWB implementation (#53)
628208d3 Merge pull request #28 from google-research/byte-addressable-memories
110598d1 Switch wishbone (#29)
70bed321 Add byte addressables memories
d55ba82f Calendar implementation with wishbone support (#25)
8eb20a36 Merge pull request #58 from google-research/elf-memsz-testing
50d99cc3 Merge pull request #60 from google-research/reuse
92596ca5 use REUSE for license compliance checks
b9e658a3 Add calendar internals (#24)
81f280b8 firmware ELF loader now handles bigger memsz properly
8ad6a290 Merge pull request #56 from google-research/remove-firmware-test-binaries
34198259 remove accidentally committed binaries, add them to gitignore
e50e56fd Move Println module (#52)
b24ecb81 Merge pull request #23 from google-research/calendar-wishbone-in
4aadb578 Upgrade to Clash 1.6.3
fb6e1998 Added calendar wishbone decoder
64aff808 Switch to GHC 9.0.2 (#51)
5f6354e9 Unit tests for ELF loader and validator, CI checks for firmware (#45)
767c7c60 Switch (#22)
e7be72e0 Initial Scatter Gather implementation (#21)
58ddbfb5 Merge pull request #36 from google-research/firmware-refactor
bbe596c5 add ELF loading code, refactor firmware code
9debf5b2 Add println-debugging for Rust code runnning on contranomy (#30)
4fd97bc0 Initial calendar implementation (#20)
dcd468dc Add doublebuffered RAM (#19)
37d8e955 Changed contranomy bounds (#27)
beb7de3a Merge pull request #26 from google-research/contranomyTestProperties
f1be5366 Changes testProperty to testPropertyNamed
8cd9f209 Merge pull request #18 from google-research/add-bittide-skeleton
873ab3d4 Pin Cabal to a specific version of Hackage
681aa48b Add Bittide project skeleton
7d8817cc Only run RISCV formal test on relevant changes (#17)
32a785a6 CI: upload riscv_formal results when verification fails (#14)
55f1d05e Add bounds to Contranomy (#13)
0179665e Add 'all' job for in-repo configurable mandatory CI checks (#15)
8ff091a4 Merge pull request #12 from google-research/add-non-altopt-tests
219d5629 Use global project cache freeze file on CI
7ceb0301 Add unit tests for ALU
6e500017 Merge pull request #8 from google-research/readd-contranomy
524f7657 Only restore `v2-` caches
b97baf59 Add documentation to wishboneStorage
88d1f604 Check all bits of func7 in definition of isM
38070586 Apply review suggestions
15734690 Add Contranomy with M and C extensions
827c9492 Add formal checking temporary directories to .gitignore
c6f33ac9 Do not install nodejs on CI
1ea4e841 Add run_test.sh for locally running a specific test
5ad5493d Only store ~/.cabal/store in CI cache
602edf12 Whitespace and other linting fixes
1c6443e9 Update copyright and license information
66f50541 Merge commit 'c3a36899b250d0e60bd9f7d365831385a457c900' as 'contranomy'
c3a36899 Squashed 'contranomy/' content from commit b604d95
963b2983 Remove `contranomy/` in preparation of adding a subtree
2caf16c1 Merge pull request #1 from google-research/rv32imc-formal
b76f15b3 Add markdown to files checked for EOL whitespace
00bbe328 Enable M extension checks on CI
903918cc Add riscv-altopts flag and use it on CI
83edf0ea Finish implementation of M and C extensions
362f8390 Merge pull request #4 from google-research/ci-cleanups
460072a8 Add whitespace linting to prevent annoying diffs
dc7a8897 Extend .gitignore with common files
b60c6e15 Add basic VSCode settings
5b8f6595 Remove accidentally added files
de0f8925 Add EOL whitespace linter
f62af151 Switch to ghcr.io
2a0e61f6 Merge pull request #2 from google-research/setup-ci
506a9704 Move scripts directory back into .github
519044a0 Merge commit '2fa2e103139feedd5438b9119f4fb460200ea686' as 'riscv-formal'
2fa2e103 Squashed 'riscv-formal/' content from commit 4f29e83
54dd1b96 Remove riscv-formal submodule
edf01bd8 Run RiscV formal in paralllel on CI
099478bd Do not run M extension formal checks
0df2fc89 Add GitHub actions workflow
6260049a Add riscv-formal submodule and configuration
7e7c6166 rv32ic formally verified with 32 bit PC.
29ef8ad2 ALU output selection fix
fdd2db66 Merge branch 'main' of https://github.com/google-research/bittide into main
484fe584 bump
fb8ed698 Change to 31 bit PC
1c5e8dd9 Update LICENSE, maintainer and copyright
390dde64 Fix .cabal file after rebase
c756bec6 Adding contranomy + extensions
ea801d4c adds disclaimer
cca34914 typos
bcffa823 initial commit
REVERT: 2eced423 Add optional VCD tracing (#41)
REVERT: 652280ad Merge pull request #39 from clash-lang/rs/jtagChainTest
REVERT: 6f1c2a20 Add JTAG chaining test.
REVERT: 72904a38 Expose JTAG output port, and move debug config into a standalone file.
REVERT: 0ac4a4f7 Merge pull request #36 from clash-lang/lucas/add-Jtag-Idle
REVERT: 31e1b754 Add `IdleCircuit` for `Jtag`
REVERT: dab50530 Bump `clash-protocols` dependency
REVERT: 390818c9 Add GHC 9.6.6 to CI (#35)
REVERT: 55ef807b Bump SBT to `1.10.1` (#34)
REVERT: e5c2b537 Merge pull request #28 from clash-lang/ffi-undefined-to-random-storable
REVERT: 4a06e476 Add randomly generated values for undefined bits in FFI
REVERT: cca33019 Merge pull request #33 from clash-lang/bumpy-wumpy-clashy-washy
REVERT: f2844c4f Bump Clash for fixed `genBitVector`
REVERT: f7ed59b2 Merge pull request #32 from clash-lang/swap-fwd-bwd
REVERT: 5bf5998e Switch `Fwd` and `Bwd` to make `M`/`S` relation consistent
REVERT: 8c7f90ae Merge pull request #29 from clash-lang/wishbone-err
REVERT: 39be9d06 Handle `ERR` in VexRiscV
REVERT: fda5b043 Merge pull request #30 from clash-lang/use-own-docker
REVERT: e15cee80 Add `--jtag-debug` option to Tasty testsuite
REVERT: 28535014 Enable JTAG tests
REVERT: a4c4a9fb Use own Docker image, add openocd
REVERT: 1156fdab Merge pull request #27 from clash-lang/enable-parallel-tests
REVERT: 06bd1d5d Merge pull request #26 from clash-lang/fpu-test-blackbox
REVERT: bb8a9bf3 Merge pull request #25 from clash-lang/parallel-jobs-makefile
REVERT: e611b53e specify number of jobs for unittests in CI
REVERT: 6a73e206 enable parallel tests
REVERT: b3d24e81 Prevent Rust from constant folding in FPU test
REVERT: 3b69ccaf Allow parallel jobs in Makefile
REVERT: 050de413 Make building OpenOCD deterministic (#23)
REVERT: 8831c6ff Merge pull request #4 from clash-lang/jtag
REVERT: 9c4ad84d remove unused code
REVERT: 3bd03ded Disable JTAG tests due to CI environment
REVERT: 44c69d12 Added HDL generation test
REVERT: bf01da02 Follow XDG standard on CI (like newer Cabals)
REVERT: 12cf4894 Connect JTAG reset out to CPU reset in, in `cpu`
REVERT: 6e0df33e Add GDB tests
REVERT: 95f15230 Style fixes by dictionary / HLint
REVERT: b0b173f6 Add dual-port storage, von Neumann architecture
REVERT: a41228bc add JTAG support to the core
REVERT: 6a0805f2 Merge pull request #17 from clash-lang/remove-simulation-hack
REVERT: 14620c85 Handle inputs and outputs in correct order
REVERT: d2428522 Eliminate need for custom `mealy`, fixing laziness
REVERT: a81bd480 Merge pull request #15 from clash-lang/bump-ghc
REVERT: 7bf9a082 Add support for GHC 9.2 and 9.4
REVERT: a651da6e Bump docker image to contain Verilator v5.020
REVERT: 4f7aefd2 Bump to NixOS 23.11
REVERT: bacce2fd Add Rust caching to CI
REVERT: 4d9eee49 Merge pull request #14 from clash-lang/single-clock-edges
REVERT: 160f05b6 add singleClockEdgedAbsolute/Relative
REVERT: 48c4f1f9 Merge pull request #11 from clash-lang/add-more-clockticks-tests
REVERT: 599d3d80 Merge pull request #13 from clash-lang/add-vscode-settings
REVERT: dd295010 Merge pull request #12 from clash-lang/add-nix-openocd
REVERT: 42c37174 Add VexRiscv's OpenOCD to Nix environment
REVERT: 49380795 Add VSCode `settings.json` to project
REVERT: dcbe306e Add more tests to ClockTicks
REVERT: 19897d8e Add more verbose versions of `clockTicks` (#10)
REVERT: e79e8083 Merge pull request #9 from clash-lang/allow-newer-clash
REVERT: b3ad455c Allow newer Clash
REVERT: e21bc165 Merge pull request #8 from clash-lang/check-vexriscv.v
REVERT: 72cf31b9 Merge pull request #7 from clash-lang/sim-hack
REVERT: 2e83fc6e Check whether committed VexRiscv.v corresponds to generated one
REVERT: 22e55412 Add direnv support
REVERT: f7617653 Add `shell.nix`
REVERT: ce8137a9 Bump GHA actions version number
REVERT: b18533a1 Use `cabal.project` in cache key calculation (#404)
REVERT: aedda1b8 Error on GHC warnings on CI
REVERT: c8ff7dcd Apply workaround to make HDL generation and simulation work
REVERT: 288d6e2d address warning about unused argument in HDL generation
REVERT: c6753672 Merge pull request #6 from clash-lang/remove-unused-import
REVERT: ac9363f3 Remove unused `Data.List` import in `VexRiscv.hs`
REVERT: 2b08a77f add newlines at EOF
REVERT: 420f75af Merge pull request #5 from clash-lang/f-extension
REVERT: 37ecabb6 minimize cache size and mark ALL addresses as IO range
REVERT: 79e53ac7 add F extension to CPU
REVERT: 47da9f87 don't use thin-archives for static library
REVERT: 96c4de06 use binary literals instead of bitPattern in storage
REVERT: 093f08fe remove git hash from generated Verilog file
REVERT: 8714ce36 let's not do bundled libraries for now :see_no_evil:
REVERT: e8b12c72 Merge pull request #2 from clash-lang/use-bundled-libs
REVERT: 884e88c7 use `extra-bundled-libraries` for verilated FFI code
REVERT: 0d02bb7f rename packages
REVERT: 1b06792c make mtvec register RW, enable ebreak test again
REVERT: cc57e814 add verilator link to README
REVERT: fd5a0d97 add README, remove bittide references
REVERT: 17e70b92 use public runner for license checks
REVERT: a9c4f4ff add REUSE checks to CI
REVERT: ecffd17e more code sharing, clean up test and sim-bin programs
REVERT: d36e959f add interconnectTwo and remove bittide dependency
REVERT: f702ff54 add storage circuit
REVERT: 3d1c4148 remove Utils.Print, move code around to make more sense
REVERT: f7c97530 remove bittide-sys dependency, remove bootloader test
REVERT: cca64d0c fix wrong wire size in blackbox
REVERT: d466dfac add CI
REVERT: cb464bb0 use `elf` crate for ELF loading
REVERT: c4535cef simplify dualPortStorage, adjust ports at call-site
REVERT: 01cad84b write custom dual-port RAM, bootloading works!
REVERT: b0c81758 add initial bootloader and payload program
REVERT: bfe0bfdf add storages for loaded programs
REVERT: 4f344f72 add vex-riscv package and integration tests
REVERT: 29084f72 Initial commit
git-subtree-dir: clash-vexriscv
git-subtree-split: 6fb0a795de77aae625b678930d15bf85428a084e
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