esp32s2-ulp-riscv-delay

This is an ESP-IDF example application exploring the clock frequency of the ESP32-S2 ULP-RISC-V coprocessor

This code relates to a help request I posted on the esp32.com forum.

Installation

$ git clone https://github.com/bitmandu/esp32s2-ulp-riscv-delay.git

Configuration

    $ idf.py set-target esp32s2
    $ idf.py menuconfig

In the Component config ⇨ ESP32S2-specific menu check:

• Enable Ultra Low Power (ULP) Coprocessor
• Enable RISC-V as ULP coprocessor

Contributing

Pull requests and issue/bug reports are very much encouraged!

License

MIT