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Aarch64 decompilation#533

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PeterMatula merged 112 commits intoavast:arm64avast/retdec:arm64from MatejKastak:arm-prepMatejKastak/retdec:arm-prepCopy head branch name to clipboardMar 28, 2019

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Commits on Sep 6, 2018

• Capstone2llvmirtool default basic modes for architectures

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Commits on Sep 10, 2018

• Base for the ARM64 translator

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Commits on Sep 11, 2018

• Fix the cs_reg_name

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• Add ARM64 support for capstone dependency

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• Temporary solution to call translate function

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• Status register and program counter added to environment

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• Methods store/load registers/operands skeletons + add instruction

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Commits on Sep 12, 2018

• Store instruction base

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Commits on Sep 13, 2018

• Operand shifts ported from ARM and MOV instruction tranlation

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Commits on Sep 15, 2018

• Arm64 - tests ported from Arm

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Commits on Sep 16, 2018

• Basic MOV tests

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Commits on Sep 20, 2018

• Test for STR instruction and test header comments

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• STP instruction + tests, pc in new enum, get op addr function

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Commits on Sep 21, 2018

• LDR + STR, LDR tests from ARM, LDP stub

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Commits on Sep 22, 2018

• Implemented parent register handling

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• LLVM data layout modified for ARM64

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Commits on Sep 23, 2018

• Removed useless debug output

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• getCarryRegister for ARM64 fixed

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• Store register ZEXT_TRUNC, 32bit tests baseline + tests

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• Zero extension tests for ADD and MOV 32bit variants

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• Implemented BL instruction

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• Implemented RET instruction

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• Implemented LDP instruction

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Commits on Sep 24, 2018

• Implemeneted ADRP instruction

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Commits on Sep 26, 2018

• enable arm64 in decompiler.py and add arm64 architecture

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• Arm64 ABI implementation

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• Arm64 decoder ported from Arm

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Commits on Sep 27, 2018

• Arm64 imm operand shifts should not update flags by default.

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• Operand register extension generator + 64bit variant extension tests

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Commits on Sep 28, 2018

• Arm64 Zero/Sign extension 32bit variant tests

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• Implemented SUB instruction

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• Implemented BR instruction

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• Arm64 syscall id register is X8

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• Specified call and return instruction ID for implemented instruction

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Commits on Jan 31, 2019

• Merge branch 'master' into arm-prep

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• Fixed compilation after merge

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• Generate pseudoasm instruction when translation routine is not found

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• Check preconditions in implemented arm64 instructions

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• Changed register generation to match other modules.

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Commits on Feb 2, 2019

• LDR instruction all 3 formats + tests

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Commits on Feb 3, 2019

• Binaries can now be decompiled

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Commits on Feb 6, 2019

• Generate condition codes for conditional instructions.

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• ARM64: strb, strh instructions + tests

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• Arm64: conditional and unconditional branch instruction + tests

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• Arm64: Instruction ret can have optional register operand + test

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• Arm64: BLR instruction + test

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Commits on Feb 7, 2019

• Arm64: CBNZ, CBZ instruction + test

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• Arm64: TBNZ, TBZ implementation + tests

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• Arm64: LDR different size variants, sign/zero extend + tests

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Commits on Feb 8, 2019

• Arm64: LDPSW instruction + tests

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• Arm64: ADC instruction + tests

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• Arm64: ADCS 32bit tests for flags

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Commits on Feb 9, 2019

• Arm64: ADR, ADRP instruction + tests

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• Arm64: AND, ANDS instruction + tests

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• Arm64: ASR instruction + tests

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• Arm64: LSL, LSR, ROR instructions + tests

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• Arm64: SUB, SBC flags + tests

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• Arm64: CMP, CMN instructions + tests

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Commits on Feb 10, 2019

• Arm64: CSEL instruction + tests

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• Arm64: CSET, CSETM instruction + tests

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Commits on Feb 11, 2019

• Arm64: MUL instruction + tests

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• Arm64: MADD instruction + tests

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• Arm64: MSUB instruction + tests

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• Arm64: MNEG instruction + tests

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• Arm64: NEG, NEGS instruction + tests

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• Arm64: NGC, NGCS initial implementation + tests

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Commits on Feb 13, 2019

• Merge branch 'master' of https://github.com/avast-tl/retdec into arm-prep

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Commits on Feb 14, 2019

• Arm64: SDIV, UDIV instruction + tests

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Commits on Feb 15, 2019

• Arm64: Fix correct semantics for SBC and NEG instructions

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• Arm64: SMADDL, UMADDL instruction + tests

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• Arm64: UMSUBL, SMSUBL instruction + tests

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• Arm64: SMNEG, UMNEG instruction + tests

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Commits on Feb 16, 2019

• Arm64: UMULL, SMULL, UMULH, SMULH instruction + tests

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• Arm64: Conditional select operation instruction + tests

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Commits on Feb 17, 2019

• Arm64: CINC, CINV, CNEG tests

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Commits on Feb 18, 2019

• Arm64: EON, EOR instruction + tests

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Commits on Feb 19, 2019

• Arm64: ORN, ORR instruction + tests

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• Arm64: TST instruction + tests

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• Arm64: EXTR instruction + tests

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Commits on Feb 20, 2019

• Arm64: Extend instructions + tests

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Commits on Feb 21, 2019

• Arm64: CCMN, CCMP instruction + tests

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Commits on Feb 22, 2019

• Arm64: NOP instruction + tests

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• Arm64: REV, RBIT, CLZ instructions + tests

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• Arm64: BIC instruction + tests

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Commits on Feb 23, 2019

• Arm64: Unpriviledged loads/stores instructions + tests

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• Arm64: Load/Store exclusive instructions + tests

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Commits on Feb 24, 2019

• ARM64: LDAXR instruction variants + tests

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• Arm64: LDAR instruction variants + tests

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Commits on Feb 27, 2019

• Arm64, llvmir-emul: don't lower bitreverse intrinsic

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Commits on Feb 28, 2019

• Arm64: FP environment + basic unary and binary operations + tests

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• Arm64: FMIN, FMINNM, FMAX, FMAXNM instruction + tests

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Commits on Mar 1, 2019

• Arm64: FCMP, FCCMP, FCVT, {U, S}CVTF instructions + tests

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• Arm64: FCVTZS, FCVTZU instructions + tests

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• Arm64, bin2llvmir: Decoder should not analyse stack.

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Commits on Mar 3, 2019

• Merge branch 'master' into arm-prep

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Commits on Mar 5, 2019

• Arm64: MOVK instruction + tests

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• Arm64: MOVN instructions + tests

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Commits on Mar 6, 2019

• Merge master with arm-prep

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Commits on Mar 7, 2019

• Architecture: Change arm architectures to account for arm64

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• Architecture: Removed the wrong architecture types

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Commits on Mar 9, 2019

• Arm64: XZR loads zero and discards result when written

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• Arm64: STR and LDR instructions now determine correct register size

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Commits on Mar 13, 2019

• Arm64: Syscall optimalization and detection

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Commits on Mar 16, 2019

• Arm64: MOVI instructions + tests, Vector and half register

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• Arm64: STR and LDR tests

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Commits on Mar 21, 2019

• Arm64: Removed zero division semantics from llvmir

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Commits on Mar 22, 2019

• Merge branch 'master' into arm-prep

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• Arm64: FMOV instruction with immediate values

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• Revert "Arm64, bin2llvmir: Decoder should not analyse stack."

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Commits on Mar 26, 2019

• Merge branch 'master' into arm-prep

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Commits on Mar 27, 2019

• Arm64: Simplified and documented some code

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• Arm64: Fixed documentation build

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