Update TVM VTA (VTA Chisel Wide memory interface) #8973
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…cc uses svOpenArrayHandle to send wide data through DPI
…le with Verilator. Jenkinsfile to have tvm_multilib_tsim defined for CPU build target.
…move verilator CPP objects from cmake config for tsim and put them as include into vta module.cc to avoid Verilator compilation warnings
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Should this PR be done to update TVM to use the latest VTA? @vegaluisjose |
vegaluisjose
approved these changes
Sep 9, 2021
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oh yeah, that is right. @tmoreau89 is this all needed right? |
ylc
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Sep 29, 2021
* VTA cmake file require Verilator include for tsim target. VTA module.cc uses svOpenArrayHandle to send wide data through DPI * Refactor Verialtor check conditions * Build TSIM only for CPU target. CPU target don't use -Werror to compile with Verilator. Jenkinsfile to have tvm_multilib_tsim defined for CPU build target. * remove build/libvta_tsim.so from non tsim targeting builds * Revert to enable TSIM build i386. Revert to -Werror in CPU config. Remove verilator CPP objects from cmake config for tsim and put them as include into vta module.cc to avoid Verilator compilation warnings * Update to latest VTA
ylc
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Jan 13, 2022
* VTA cmake file require Verilator include for tsim target. VTA module.cc uses svOpenArrayHandle to send wide data through DPI * Refactor Verialtor check conditions * Build TSIM only for CPU target. CPU target don't use -Werror to compile with Verilator. Jenkinsfile to have tvm_multilib_tsim defined for CPU build target. * remove build/libvta_tsim.so from non tsim targeting builds * Revert to enable TSIM build i386. Revert to -Werror in CPU config. Remove verilator CPP objects from cmake config for tsim and put them as include into vta module.cc to avoid Verilator compilation warnings * Update to latest VTA
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Update TVM to point to the latest VTA. VTA Chisel wide memory interface