[BugFix][TIR][Schedule] TileWithTensorIntrin skip ComputeInline if bu… #17440
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…ffer not padded by PadEinsum
TileWithTensorIntrininsrc/tir/schedule/transform.cccallsPadEinsumand inlines the padded input (output) to its original producer (consumer). However it is possible that one of the inputs/outputs does not need to be padded, in which case that producer (consumer) is not padded byPadEinsum. This means thatTileWithTensorIntrinmay inline blocks that are irrelevant to padding and must not be inlined.This has led to multiple bug reports and (temporary) fixes as in #17171, #16614, #16239 and #15505. Unfortunately #16239 and #17171 can only prevent TVM from crashing when the padded buffer is an input/output buffer, and still some incorrect inlining may be performed. The workaround in #15505 tried to handle this bug by extra checking in the
MultiLevelTilingTensorCorerule, which is logically incorrect. This PR aims to provide a one-and-for-all fix for this.Credit to @XFPlus for the bug reproduce example in #16239.