[TIR][Hexagon] Enhancement of NarrowDataType pass for binary ops #14298
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This is enhancement of PR#13327.
Motivation:
Playing with MetaScheduler for Hexagon target it was found that
avg_pool2d has rather poor performance due to lack of vectorized code.
IndexDataTypeNormalizer pass converts all indices to int64 format and
NarrowDataTypeRewriter should do the opposite (back to int32). In case of fail,
we have a lot of int64 arithmetic for average pooling that can not be
vectorized.
What was done:
Added support of binary ops ("div", "max", "min", "+" etc.) in
NarrowDataTypeRewriter. In case of different bitwidth of operands in
binary opeation it does downcasting instead of upcasting (as it was
before).
Performance impact:
avg_pool2d from quantized InceptionV3 with the shape [1, 8, 35, 35, 32]
(NCHW32c layout) tuned with MetaScheduler on Snapdragon 8gen1:
shape | Before fix, ms | After fix, ms | speedup |
------------------|----------------|---------------|-------------|
avg_pool2d, int32 | 6.67 | 4.41 | +34% |
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masahi
approved these changes
Mar 15, 2023
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This is enhancement of PR#13327.
Motivation:
Playing with MetaScheduler for Hexagon target it was found that
avg_pool2dhas rather poor performance due to lack of vectorized code.IndexDataTypeNormalizerpass converts all indices to "int64" format andNarrowDataTypeRewritershould do the opposite (back to "int32"). In case of fail, we have a lot of int64 arithmetic for average pooling that can not be vectorized.What was done:
Added support of binary ops ("div", "max", "min", "+" etc.) in
NarrowDataTypeRewriter. In case of different bitwidth of operands in binary opeation it does downcasting instead of upcasting (as it was before).Performance impact:
avg_pool2dfrom quantized InceptionV3 with the shape [1, 8, 35, 35, 32] (NCHW32c layout) tuned with MetaScheduler on Snapdragon 8gen1: