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[VTA] Refactor to increase platform coverage (Ultra96 etc.) (#3496)
* hardware refactor for increased FPGA coverage, small optimizations * fix header * cleaning up parameters that won't be needed for now * streamlining makefile, and simplifying tcl scripts * moving parameter derivation into pkg_config.py, keeping tcl scripts lightweight * refactoring tcl script to avoid global variables * deriving AXI signals in pkg_config.py * unifying address map definition for hardware and software drivers * single channel design for ultra96 to simplify build * enable alu by default, no mul opcode for now * hardware fix * new bitstream; vta version * avoid error when env variable is not set * ultra96 cleanup * further cleaning up tcl script for bitstream generation * preliminary rpc server support on ultra96 * rpc server tracker scripts * ultra96 ldflag * ultra96 support * ultra96 support * cleanup line * cmake support for ultra96 * simplify memory instantiation * cleaning up IP parameter initialization * fix queue instantiation * 2019.1 transition * fix macro def * removing bus width from config * cleanup * fix * turning off testing for now * cleanup ultra96 ps insantiation * minor refactor * adding comments * upgrading to tophub v0.6 * model used in TVM target now refers to a specific version of VTA for better autoTVM scheduling * revert change due to bug * rename driver files to be for zynq-type devices * streamlining address mapping * unifying register map offset values between driver and hardware generator * rely on cma library for cache flush/invalidation * coherence management * not make buffer packing depend on data types that can be wider than 64bits * refactor config derivation to minimize free parameters * fix environment/pkg config interaction * adding cfg dump property to pkgconfig: * fix rpc reconfig * fix spacing * cleanup * fix spacing * long line fix * fix spacing and lint * fix line length * cmake fix * environment fix * renaming after pynq since the driver stack relies on the pynq library - see pynq.io * update doc * adding parameterization to name * space * removing reg width * vta RPC * update doc on how to edit vta_config.json * fix path * fix path
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,17 +1,13 @@ | ||
{ | ||
"TARGET" : "pynq", | ||
"HW_FREQ" : 100, | ||
"HW_CLK_TARGET" : 8, | ||
"HW_VER" : "0.0.0", | ||
"HW_VER" : "0.0.1", | ||
"LOG_INP_WIDTH" : 3, | ||
"LOG_WGT_WIDTH" : 3, | ||
"LOG_ACC_WIDTH" : 5, | ||
"LOG_OUT_WIDTH" : 3, | ||
"LOG_BATCH" : 0, | ||
"LOG_BLOCK_IN" : 4, | ||
"LOG_BLOCK_OUT" : 4, | ||
"LOG_BLOCK" : 4, | ||
"LOG_UOP_BUFF_SIZE" : 15, | ||
"LOG_INP_BUFF_SIZE" : 15, | ||
"LOG_INP_BUFF_SIZE" :15, | ||
"LOG_WGT_BUFF_SIZE" : 18, | ||
"LOG_ACC_BUFF_SIZE" : 17 | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,13 @@ | ||
{ | ||
"TARGET" : "ultra96", | ||
"HW_VER" : "0.0.1", | ||
"LOG_INP_WIDTH" : 3, | ||
"LOG_WGT_WIDTH" : 3, | ||
"LOG_ACC_WIDTH" : 5, | ||
"LOG_BATCH" : 0, | ||
"LOG_BLOCK" : 4, | ||
"LOG_UOP_BUFF_SIZE" : 15, | ||
"LOG_INP_BUFF_SIZE" :15, | ||
"LOG_WGT_BUFF_SIZE" : 18, | ||
"LOG_ACC_BUFF_SIZE" : 17 | ||
} |
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