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1. aneels3.github.io aneels3.github.io Public

   CSS

2. AES-128 AES-128 Public

   Single pipeline AES 128 bit encryption using S-box as Look up table.

   Verilog 4 3

3. chipsalliance/riscv-dv chipsalliance/riscv-dv Public

   Random instruction generator for RISC-V processor verification

   Python 1k 329

4. verible verible Public

   Forked from chipsalliance/verible

   Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

   C++

5. pyvsc pyvsc Public

   Forked from fvutils/pyvsc

   Python packages providing a library for Verification Stimulus and Coverage

   Python