Programmable Logic
- current_bd_design design_1
- write_bd_tcl -hier_blks [get_bd_cells design_1] design_1.tcl
- current_bd_design design_2
- source design_1.tcl
Block Design
andreisilv/GNSS-FPGA
Folders and files
| Name | Name | Last commit date | ||
|---|---|---|---|---|
Repository files navigation