Working in simulation but incorrect synthesis output?

[bretthannigan]

The combinatorial LFSR module works perfectly in the following testbench:

`timescale 1ns/1ns
`include "../rtl/lfsr.v"
module lfsr_tb();

reg [7:0] data_in;
reg [31:0] state_in;
wire [7:0] data_out;
wire [31:0] state_out;

lfsr #(
    .LFSR_WIDTH(32),
    .LFSR_POLY(32'h4C11DB7),
    .LFSR_CONFIG("GALOIS"),
    .REVERSE(0),
    .DATA_WIDTH(8),
    .STYLE("REDUCTION")
) DUT (
    .data_in(8'h01),
    .state_in(32'hFFFFFFFF),
    .data_out(data_out),
    .state_out(state_out)
);

initial
begin
    state_in = 32'hFFFFFFFF;
    data_in = 8'h01;
end

initial
    #400 $stop;

initial 
begin
    $dumpfile("out.vcd");
    $dumpvars(0,DUT);
end

endmodule

I obtain the output state_out = 0x4AC9A203, which is correct compared to an online CRC-32 calculator. When I use the following code to synthesize and program an iCE40HX-8K device using the IceStorm toolchain, the output is different.

`include "lfsr.v"
module top (clk, o_led);

    input wire clk;
    output wire [7:0] o_led;
    wire [31:0] state;

    lfsr #(
        .LFSR_WIDTH(32),
        .LFSR_POLY(32'h4C11DB7),
        .LFSR_CONFIG("GALOIS"),
        .REVERSE(0),
        .DATA_WIDTH(8),
        .STYLE("REDUCTION")
    ) crc (
        .data_in(8'h01),
        .state_in(32'hFFFFFFFF),
        .data_out(),
        .state_out(state)
    );
    assign o_led = state[31:24];

endmodule

I now obtain state_out = 0x4E08BFB4 from the hardware. Interestingly, I get the correct results when .data_in(FF). Also (may be unrelated), synthesis does not complete with .STYLE("LOOP"), failing on the error:
ERROR: Conflicting init values for signal 1'0 (\crc.i [0] = 1'1, \crc.data_out_reg [0] = 1'0).

Has anyone got this to work correctly on this FPGA/toolchain?

[alexforencich]

Sounds like a yosys bug of some sort. Synplify also has issues. This code works in ISE, Vivado, Quartus Prime, and Quartus Prime Pro.

[bretthannigan]

Okay, I have fixed the issue and it was quite simple. I removed the initialization to zero of state_val and data_val in lines 208 and 209 of lfsr.v. With this change the yosys iCE40 output matches simulation and an online CRC calculator. Next, to solve the issue of LOOP style not synthesizing, I made similar changes to lines 398 and 399 as well as defined new integer variables for i and j in the for loops as Yosys seems not to scope the loop indices correctly. Not sure why this fixes it but it works for me now.

[alexforencich]

Very odd. Well, at some point I need to look in to rewriting this module to use a constant function instead of the initial block so that synplify is happy. I have had several people complain about that, IMO it's a synplify bug as most other tools are perfectly fine with constant elaboration from initial blocks. I mainly need to make sure it that will still work in ISE. But if all that looks good, then presumably yosys will also be happy with that.

[alexforencich]

Alright, I think I finally have a rewrite done that uses constant functions instead of initial blocks, and also does some other reorganizing. Please let me know if it works any better in Yosys. I need to do some more testing, but so far it looks like it works in ISE, Vivado, Quartus Prime, and Quartus Prime Pro.