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1. DLX-Project DLX-Project Public

   DLX processor implementation in VHDL

   Verilog

2. MSLabs MSLabs Public

   Hardware Design and Synthesis exercises

   VHDL

3. doreado/isa2324-labs doreado/isa2324-labs Public

   Laboratory exercises from Integrated Systems Architecture course.

   Verilog

4. doreado/camPUF doreado/camPUF Public

   camPUF implementation

   Python

5. Lelezinski/buffer-overflow-demo Lelezinski/buffer-overflow-demo Public

   Operating Systems for Embedded Systems A.Y. 2022/23 group project: a Privilege Escalation demonstration exploiting Buffer Overflow.

   C 1

6. Tarta56/cv32e40p_tftlab_fault_tolerance_assignment Tarta56/cv32e40p_tftlab_fault_tolerance_assignment Public

   Forked from cad-polito-it/cv32e40p_tftlab

   CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

   SystemVerilog