[oliviergaraud]

What?

Compute globally unique device IDs for object storage descriptors in both allocateMemory and exchangeIOV.

Why?

The device ID passed to initBasicDescObj was the inner loop index (i or iov.devId), so every thread generated the same set of IDs (e.g. {0, 1, 2}).

This could route all threads through the same backend connection, defeating multi-threaded parallelism.
Additionally, devidx was never incremented in the OBJ branch of exchangeIOV, so all remote descriptors used device ID 0.

How?

In both allocateMemory (local side) and exchangeIOV (remote side), compute the device ID as list_idx * num_devices + inner_idx, producing unique IDs across all threads (e.g. thread 0 gets {0,1,2}, thread 1 gets {3,4,5}).
Also add the missing devidx++ in exchangeIOV so the remote descriptors stay in sync with local ones.

Summary by CodeRabbit

• Chores
  • Improved internal benchmark device mapping to tie resources more consistently to both worker slices and devices.
  • Refined remote IO descriptor construction to use explicit per-slice/per-device indexing.
  • Reduced mapping-related inconsistencies in multi-device benchmark runs to improve reliability and predictability.

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[github-actions]

👋 Hi oliviergaraud! Thank you for contributing to ai-dynamo/nixl.

Your PR reviewers will review your contribution then trigger the CI to test your changes.

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[coderabbitai]

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📝 Walkthrough

Walkthrough

This PR updates OBJ-storage paths to compute composite device IDs as list_idx * num_devices + device_idx in allocateMemory and exchangeIOV, and passes that obj_dev_id (while retaining iov.len and iov.metaInfo) to initBasicDescObj.

Changes

OBJ Device ID Mapping Refactor

Layer / File(s)	Summary
Composite device ID calculation in allocation and IO exchange benchmark/nixlbench/src/worker/nixl/nixl_worker.cpp	allocateMemory and exchangeIOV compute obj_dev_id = list_idx * num_devices + device_idx and pass it to initBasicDescObj; exchangeIOV uses iov.len and iov.metaInfo for object size/name instead of relying on iov.devId.

🎯 2 (Simple) | ⏱️ ~8 minutes

Suggested reviewers:

• aranadive
• ovidiusm
• ofer
• brminich

"A rabbit hops through code tonight,
counting lists and devices just right,
list times devices—IDs align,
object names and sizes fine,
a neat little hop and all's in sight." 🐰✨

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title clearly and specifically describes the main change: fixing device ID collisions in object storage across threads.
Description check	✅ Passed	The description includes all required template sections (What, Why, How) with clear, detailed explanations of the problem and solution.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.

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✨ Finishing Touches

🧪 Generate unit tests (beta)

• Create PR with unit tests

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[aranadive]

/ok to test 1a2d02f

[aranadive]

/build

[oliviergaraud]

Thanks @aranadive
I cannot access the pages to see what's wrong with the tests that fail, how can I move forward ?
http://nbuprod.blsm.nvidia.com/nbu-swx-nixl-main/blue/organizations/jenkins/nixl-ci-dl-gpu/detail/nixl-ci-dl-gpu/621/pipeline/
http://nbuprod.blsm.nvidia.com/nbu-swx-nixl-main/blue/organizations/jenkins/nixl-ci-gpu/detail/nixl-ci-gpu/1860/pipeline/

[ofer]

/ok to test 1a2d02f

[aranadive]

Thanks @aranadive I cannot access the pages to see what's wrong with the tests that fail, how can I move forward ? http://nbuprod.blsm.nvidia.com/nbu-swx-nixl-main/blue/organizations/jenkins/nixl-ci-dl-gpu/detail/nixl-ci-dl-gpu/621/pipeline/ http://nbuprod.blsm.nvidia.com/nbu-swx-nixl-main/blue/organizations/jenkins/nixl-ci-gpu/detail/nixl-ci-gpu/1860/pipeline/

Yeah those are not visible outside of our org. For now they are unrelated to the PR. We will triage and let you know if its a PR issue.

[ofer]

/build

[ofer]

@oliviergaraud please rebase to pick up some CI fixes

[oliviergaraud]

@oliviergaraud please rebase to pick up some CI fixes

done.

[ofer]

/ok to test dd79daf

[ofer]

/build

[ofer]

/build