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1. Single-Cycle-Miroprocessor_MIPS-ISA Single-Cycle-Miroprocessor_MIPS-ISA Public

   Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.

   Verilog

2. Memory-Verification-using-UVM Memory-Verification-using-UVM Public

   Verification of Memory Using Class Based Environment and UVM Environment.

   SystemVerilog

3. UART-Verilog-Design UART-Verilog-Design Public

   Design and Verification of UART IP that allows serial communication between two systems.

   Verilog

4. Design-Verification-FIFO_IP Design-Verification-FIFO_IP Public

   This project focuses on the design and verification of FIFOs, which is essential in digital systems for managing data flow between different components.

   SystemVerilog

5. ALU-Design-Verification_UVM ALU-Design-Verification_UVM Public

   Verification of a 32-bit Arithmetic Logic Unit (ALU) using Universal Verification Methodology (UVM).

   SystemVerilog

6. AES-128-Encryption-Verification AES-128-Encryption-Verification Public

   Verification of Advanced Encryption Standard (AES-128) Using the Universal Verification Methodology (UVM).

   Verilog