WIP: NIXL layer-identity transfer mapping

[ZhanqiuHu]

Layer-name-keyed NIXL transfer mapping for P/D configs with different KV groupings.

Base: vllm-project#58207 + vllm-project#58380, with TP-invariant connector planning removed.

Validated: Qwen3.6-35B-A3B-FP8 + DFlash, TP2 P (17 groups, draft block 640) → TP4 D (5 groups, block 1280), LBHNC, TRITON_ATTN, pull transfer, PP/DCP/PCP=1, no prefix caching. GSM8K 1319 examples: strict EM 0.9545, flexible 0.9515. Validation config also used --max-num-seqs 32 --mamba-cache-dtype bfloat16 --mamba-ssm-cache-dtype bfloat16 (from vllm-project#58380 benchmark methodology; the dtype overrides the model's mamba_ssm_dtype='float32').

Prefill

VLLM_KV_CACHE_LAYOUT=LBHNC VLLM_SSM_CONV_STATE_LAYOUT=DS VLLM_USE_V2_MODEL_RUNNER=1 \
VLLM_NIXL_EXPERIMENTAL_LAYER_MAPPING=1 \
vllm serve Qwen/Qwen3.6-35B-A3B-FP8 \
  --device-ids 0,1 --port 8000 --tensor-parallel-size 2 \
  --kv-transfer-config '{"kv_connector":"NixlConnector","kv_role":"kv_producer","kv_load_failure_policy":"fail"}' \
  --served-model-name zhu-pddev-q36-lb-p640d1280-1009 \
  --block-size 640 \
  --attention-backend TRITON_ATTN \
  --speculative-config '{"model":"z-lab/Qwen3.6-35B-A3B-DFlash","method":"dflash","num_speculative_tokens":7,"attention_backend":"TRITON_ATTN"}' \
  --no-enable-prefix-caching

Decode

VLLM_KV_CACHE_LAYOUT=LBHNC VLLM_SSM_CONV_STATE_LAYOUT=DS VLLM_USE_V2_MODEL_RUNNER=1 \
VLLM_NIXL_EXPERIMENTAL_LAYER_MAPPING=1 \
vllm serve Qwen/Qwen3.6-35B-A3B-FP8 \
  --device-ids 0,1,2,3 --port 8200 --tensor-parallel-size 4 \
  --kv-transfer-config '{"kv_connector":"NixlConnector","kv_role":"kv_consumer","kv_load_failure_policy":"fail"}' \
  --served-model-name zhu-pddev-q36-lb-p640d1280-1009 \
  --block-size 1280 \
  --attention-backend TRITON_ATTN \
  --speculative-config '{"model":"z-lab/Qwen3.6-35B-A3B-DFlash","method":"dflash","num_speculative_tokens":7,"attention_backend":"TRITON_ATTN"}' \
  --no-enable-prefix-caching

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