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[driver] upgrade to new clk driver
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SamulKyull authored and SamulKyull committed Nov 10, 2024
1 parent 44130c0 commit 4aa4714
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Showing 173 changed files with 849 additions and 14,568 deletions.
6 changes: 3 additions & 3 deletions board/100ask-d1-h/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,10 @@ sunxi_serial_t uart_dbg = {
},
.uart_clk = {
.gate_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.gate_reg_offset = 0,
.gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET,
.rst_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.rst_reg_offset = 16,
.parent_clk = 24000000,
.rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET,
.parent_clk = SERIAL_DEFAULT_PARENT_CLK,
},
};

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15 changes: 11 additions & 4 deletions board/100ask-ros/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -33,10 +33,10 @@ sunxi_serial_t uart_dbg = {
},
.uart_clk = {
.gate_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.gate_reg_offset = 0,
.gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET,
.rst_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.rst_reg_offset = 16,
.parent_clk = 24000000,
.rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET,
.parent_clk = SERIAL_DEFAULT_PARENT_CLK,
},
};

Expand All @@ -62,11 +62,18 @@ sdhci_t sdhci0 = {
sunxi_i2c_t i2c_pmu = {
.base = SUNXI_RTWI_BASE,
.id = SUNXI_R_I2C0,
.speed = 4000000,
.speed = SUNXI_I2C_SPEED_400K,
.gpio = {
.gpio_scl = {GPIO_PIN(GPIO_PORTL, 0), GPIO_PERIPH_MUX2},
.gpio_sda = {GPIO_PIN(GPIO_PORTL, 1), GPIO_PERIPH_MUX2},
},
.i2c_clk = {
.gate_reg_base = CCU_BASE + CCU_TWI_BGR_REG,
.gate_reg_offset = TWI_DEFAULT_CLK_GATE_OFFSET + 0,
.rst_reg_base = CCU_BASE + CCU_TWI_BGR_REG,
.rst_reg_offset = TWI_DEFAULT_CLK_RST_OFFSET + 0,
.parent_clk = 24000000,
},
};

void clean_syterkit_data(void) {
Expand Down
60 changes: 51 additions & 9 deletions board/100ask-t113i/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -12,29 +12,71 @@

#include <mmu.h>

#include <sys-dram.h>
#include <sys-gpio.h>
#include <sys-sdcard.h>
#include <sys-dram.h>
#include <sys-spi.h>
#include <sys-uart.h>

sunxi_serial_t uart_dbg = {
.base = SUNXI_UART0_BASE,
.id = 0,
.gpio_tx = {GPIO_PIN(GPIO_PORTB, 8), GPIO_PERIPH_MUX6},
.gpio_rx = {GPIO_PIN(GPIO_PORTB, 9), GPIO_PERIPH_MUX6},
.baud_rate = UART_BAUDRATE_115200,
.dlen = UART_DLEN_8,
.stop = UART_STOP_BIT_0,
.parity = UART_PARITY_NO,
.gpio_pin = {
.gpio_tx = {GPIO_PIN(GPIO_PORTB, 8), GPIO_PERIPH_MUX6},
.gpio_rx = {GPIO_PIN(GPIO_PORTB, 9), GPIO_PERIPH_MUX6},
},
.uart_clk = {
.gate_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET,
.rst_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET,
.parent_clk = SERIAL_DEFAULT_PARENT_CLK,
},
};

sunxi_dma_t sunxi_dma = {
.dma_reg_base = SUNXI_DMA_BASE,
.bus_clk = {
.gate_reg_base = CCU_BASE + CCU_MBUS_MAT_CLK_GATING_REG,
.gate_reg_offset = DMA_DEFAULT_CLK_GATE_OFFSET,
},
.dma_clk = {
.rst_reg_base = CCU_BASE + CCU_DMA_BGR_REG,
.rst_reg_offset = DMA_DEFAULT_CLK_RST_OFFSET,
.gate_reg_base = CCU_BASE + CCU_DMA_BGR_REG,
.gate_reg_offset = DMA_DEFAULT_CLK_GATE_OFFSET,
},
};

sunxi_spi_t sunxi_spi0 = {
.base = SUNXI_SPI0_BASE,
.id = 0,
.clk_rate = 75 * 1000 * 1000,
.gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4},
.gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4},
.gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4},
.gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4},
.gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4},
.gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4},
.gpio = {
.gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4},
.gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4},
.gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4},
.gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4},
.gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4},
.gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4},
},
.spi_clk = {
.spi_clock_cfg_base = CCU_BASE + CCU_SPI0_CLK_REG,
.spi_clock_factor_n_offset = SPI_CLK_SEL_FACTOR_N_OFF,
.spi_clock_source = SPI_CLK_SEL_PERIPH_300M,
},
.parent_clk_reg = {
.rst_reg_base = CCU_BASE + CCU_SPI_BGR_REG,
.rst_reg_offset = SPI_DEFAULT_CLK_RST_OFFSET + 0,
.gate_reg_base = CCU_BASE + CCU_SPI_BGR_REG,
.gate_reg_offset = SPI_DEFAULT_CLK_GATE_OFFSET + 0,
.parent_clk = 300000000,
},
.dma_handle = &sunxi_dma,
};

sdhci_t sdhci0 = {
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64 changes: 53 additions & 11 deletions board/100ask-t113s3/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7,34 +7,76 @@

#include <common.h>

#include <sys-clk.h>
#include <reg-ncat.h>
#include <sys-clk.h>

#include <mmu.h>

#include <sys-dram.h>
#include <sys-gpio.h>
#include <sys-sdcard.h>
#include <sys-spi.h>
#include <sys-uart.h>
#include <sys-dram.h>
#include <sys-sdcard.h>

sunxi_serial_t uart_dbg = {
.base = SUNXI_UART3_BASE,
.id = 3,
.gpio_tx = {GPIO_PIN(GPIO_PORTB, 6), GPIO_PERIPH_MUX7},
.gpio_rx = {GPIO_PIN(GPIO_PORTB, 7), GPIO_PERIPH_MUX7},
.baud_rate = UART_BAUDRATE_115200,
.dlen = UART_DLEN_8,
.stop = UART_STOP_BIT_0,
.parity = UART_PARITY_NO,
.gpio_pin = {
.gpio_tx = {GPIO_PIN(GPIO_PORTB, 6), GPIO_PERIPH_MUX7},
.gpio_rx = {GPIO_PIN(GPIO_PORTB, 7), GPIO_PERIPH_MUX7},
},
.uart_clk = {
.gate_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET + 3,
.rst_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET + 3,
.parent_clk = SERIAL_DEFAULT_PARENT_CLK,
},
};

sunxi_dma_t sunxi_dma = {
.dma_reg_base = SUNXI_DMA_BASE,
.bus_clk = {
.gate_reg_base = CCU_BASE + CCU_MBUS_MAT_CLK_GATING_REG,
.gate_reg_offset = DMA_DEFAULT_CLK_GATE_OFFSET,
},
.dma_clk = {
.rst_reg_base = CCU_BASE + CCU_DMA_BGR_REG,
.rst_reg_offset = DMA_DEFAULT_CLK_RST_OFFSET,
.gate_reg_base = CCU_BASE + CCU_DMA_BGR_REG,
.gate_reg_offset = DMA_DEFAULT_CLK_GATE_OFFSET,
},
};

sunxi_spi_t sunxi_spi0 = {
.base = SUNXI_SPI0_BASE,
.id = 0,
.clk_rate = 75 * 1000 * 1000,
.gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4},
.gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4},
.gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4},
.gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4},
.gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4},
.gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4},
.gpio = {
.gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4},
.gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4},
.gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4},
.gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4},
.gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4},
.gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4},
},
.spi_clk = {
.spi_clock_cfg_base = CCU_BASE + CCU_SPI0_CLK_REG,
.spi_clock_factor_n_offset = SPI_CLK_SEL_FACTOR_N_OFF,
.spi_clock_source = SPI_CLK_SEL_PERIPH_300M,
},
.parent_clk_reg = {
.rst_reg_base = CCU_BASE + CCU_SPI_BGR_REG,
.rst_reg_offset = SPI_DEFAULT_CLK_RST_OFFSET + 0,
.gate_reg_base = CCU_BASE + CCU_SPI_BGR_REG,
.gate_reg_offset = SPI_DEFAULT_CLK_GATE_OFFSET + 0,
.parent_clk = 300000000,
},
.dma_handle = &sunxi_dma,
};

sdhci_t sdhci0 = {
Expand Down
2 changes: 1 addition & 1 deletion board/100ask-t113s3/usb_test/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ int main(void) {
/* Dump information about the system clocks. */
sunxi_clk_dump();

sunxi_dma_init();


sunxi_dma_test((uint32_t *) 0x41008000, (uint32_t *) 0x40008000);

Expand Down
90 changes: 74 additions & 16 deletions board/avaota-a1/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,21 @@
sunxi_serial_t uart_dbg = {
.base = SUNXI_UART0_BASE,
.id = 0,
.gpio_tx = {GPIO_PIN(GPIO_PORTB, 9), GPIO_PERIPH_MUX2},
.gpio_rx = {GPIO_PIN(GPIO_PORTB, 10), GPIO_PERIPH_MUX2},
.baud_rate = UART_BAUDRATE_115200,
.dlen = UART_DLEN_8,
.stop = UART_STOP_BIT_0,
.parity = UART_PARITY_NO,
.gpio_pin = {
.gpio_tx = {GPIO_PIN(GPIO_PORTB, 9), GPIO_PERIPH_MUX2},
.gpio_rx = {GPIO_PIN(GPIO_PORTB, 10), GPIO_PERIPH_MUX2},
},
.uart_clk = {
.gate_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET,
.rst_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET,
.parent_clk = SERIAL_DEFAULT_PARENT_CLK,
},
};

sunxi_serial_t uart_dbg_1m5 = {
Expand All @@ -35,20 +48,58 @@ sunxi_serial_t uart_dbg_1m5 = {
.dlen = UART_DLEN_8,
.stop = UART_STOP_BIT_0,
.parity = UART_PARITY_NO,
.gpio_tx = {GPIO_PIN(GPIO_PORTB, 9), GPIO_PERIPH_MUX2},
.gpio_rx = {GPIO_PIN(GPIO_PORTB, 10), GPIO_PERIPH_MUX2},
.gpio_pin = {
.gpio_tx = {GPIO_PIN(GPIO_PORTB, 9), GPIO_PERIPH_MUX2},
.gpio_rx = {GPIO_PIN(GPIO_PORTB, 10), GPIO_PERIPH_MUX2},
},
.uart_clk = {
.gate_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET,
.rst_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET,
.parent_clk = SERIAL_DEFAULT_PARENT_CLK,
},
};

sunxi_dma_t sunxi_dma = {
.dma_reg_base = SUNXI_DMA_BASE,
.bus_clk = {
.gate_reg_base = CCU_BASE + CCU_MBUS_MAT_CLK_GATING_REG,
.gate_reg_offset = DMA_DEFAULT_CLK_GATE_OFFSET,
},
.dma_clk = {
.rst_reg_base = CCU_BASE + CCU_DMA_BGR_REG,
.rst_reg_offset = DMA_DEFAULT_CLK_RST_OFFSET,
.gate_reg_base = CCU_BASE + CCU_DMA_BGR_REG,
.gate_reg_offset = DMA_DEFAULT_CLK_GATE_OFFSET,
},
};

sunxi_spi_t sunxi_spi0 = {
.base = SUNXI_SPI0_BASE,
.id = 0,
.clk_rate = 75 * 1000 * 1000,
.gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4},
.gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4},
.gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4},
.gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4},
.gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4},
.gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4},
.gpio = {
.gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4},
.gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4},
.gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4},
.gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4},
.gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4},
.gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4},
},
.spi_clk = {
.spi_clock_cfg_base = CCU_BASE + CCU_SPI0_CLK_REG,
.spi_clock_factor_n_offset = SPI_CLK_SEL_FACTOR_N_OFF,
.spi_clock_source = SPI_CLK_SEL_PERIPH_300M,
},
.parent_clk_reg = {
.rst_reg_base = CCU_BASE + CCU_SPI_BGR_REG,
.rst_reg_offset = SPI_DEFAULT_CLK_RST_OFFSET + 0,
.gate_reg_base = CCU_BASE + CCU_SPI_BGR_REG,
.gate_reg_offset = SPI_DEFAULT_CLK_GATE_OFFSET + 0,
.parent_clk = 300000000,
},
.dma_handle = &sunxi_dma,
};

sunxi_sdhci_t sdhci0 = {
Expand Down Expand Up @@ -99,13 +150,21 @@ sunxi_sdhci_t sdhci2 = {
},
};


sunxi_i2c_t i2c_pmu = {
.base = SUNXI_R_TWI0_BASE,
.base = SUNXI_RTWI_BASE,
.id = SUNXI_R_I2C0,
.speed = 4000000,
.gpio_scl = {GPIO_PIN(GPIO_PORTL, 0), GPIO_PERIPH_MUX2},
.gpio_sda = {GPIO_PIN(GPIO_PORTL, 1), GPIO_PERIPH_MUX2},
.speed = SUNXI_I2C_SPEED_400K,
.gpio = {
.gpio_scl = {GPIO_PIN(GPIO_PORTL, 0), GPIO_PERIPH_MUX2},
.gpio_sda = {GPIO_PIN(GPIO_PORTL, 1), GPIO_PERIPH_MUX2},
},
.i2c_clk = {
.gate_reg_base = SUNXI_RTWI_BRG_REG,
.gate_reg_offset = TWI_DEFAULT_CLK_GATE_OFFSET + 0,
.rst_reg_base = SUNXI_RTWI_BRG_REG,
.rst_reg_offset = TWI_DEFAULT_CLK_RST_OFFSET + 0,
.parent_clk = 24000000,
},
};

enum dram_training_type {
Expand Down Expand Up @@ -189,7 +248,6 @@ void clean_syterkit_data(void) {
}

void rtc_set_vccio_det_spare(void) {

}

void set_rpio_power_mode(void) {
Expand Down
30 changes: 20 additions & 10 deletions board/avaota-a1/extlinux_boot/spi_lcd.c
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Original file line number Diff line number Diff line change
Expand Up @@ -48,18 +48,30 @@
#define SPI_LCD_COLOR_CYAN 0x7FFF
#define SPI_LCD_COLOR_YELLOW 0xFFE0

extern sunxi_dma_t sunxi_dma;

static sunxi_spi_t sunxi_spi0_lcd = {
.base = SUNXI_R_SPI_BASE,
.clk_reg = {
.ccu_base = SUNXI_R_PRCM_BASE,
.spi_clk_reg_offest = SUNXI_S_SPI_CLK_REG,
.spi_bgr_reg_offset = SUNXI_S_SPI_BGR_REG,
},
.id = 0,
.clk_rate = 75 * 1000 * 1000,
.gpio_cs = {GPIO_PIN(GPIO_PORTL, 10), GPIO_PERIPH_MUX6},
.gpio_sck = {GPIO_PIN(GPIO_PORTL, 11), GPIO_PERIPH_MUX6},
.gpio_mosi = {GPIO_PIN(GPIO_PORTL, 12), GPIO_PERIPH_MUX6},
.gpio = {
.gpio_cs = {GPIO_PIN(GPIO_PORTL, 10), GPIO_PERIPH_MUX6},
.gpio_sck = {GPIO_PIN(GPIO_PORTL, 11), GPIO_PERIPH_MUX6},
.gpio_mosi = {GPIO_PIN(GPIO_PORTL, 12), GPIO_PERIPH_MUX6},
},
.spi_clk = {
.spi_clock_cfg_base = SUNXI_R_PRCM_BASE + SUNXI_S_SPI_CLK_REG,
.spi_clock_factor_n_offset = SPI_CLK_SEL_FACTOR_N_OFF,
.spi_clock_source = SPI_CLK_SEL_PERIPH_300M,
},
.parent_clk_reg = {
.rst_reg_base = SUNXI_R_PRCM_BASE + SUNXI_S_SPI_BGR_REG,
.rst_reg_offset = SPI_DEFAULT_CLK_RST_OFFSET + 0,
.gate_reg_base = SUNXI_R_PRCM_BASE + SUNXI_S_SPI_BGR_REG,
.gate_reg_offset = SPI_DEFAULT_CLK_GATE_OFFSET + 0,
.parent_clk = 300000000,
},
.dma_handle = &sunxi_dma,
};

static gpio_mux_t lcd_dc_pins = {
Expand Down Expand Up @@ -149,8 +161,6 @@ static void LCD_Init(void) {
sunxi_gpio_init(lcd_res_pins.pin, lcd_res_pins.mux);
sunxi_gpio_init(lcd_blk_pins.pin, lcd_blk_pins.mux);

sunxi_dma_init();

if (sunxi_spi_init(&sunxi_spi0_lcd) != 0) {
printk_error("SPI: init failed\n");
}
Expand Down
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