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Module parameters are not affected by setundef pass #4732

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kamilrakoczy opened this issue Nov 12, 2024 · 0 comments · May be fixed by #4733
Open

Module parameters are not affected by setundef pass #4732

kamilrakoczy opened this issue Nov 12, 2024 · 0 comments · May be fixed by #4733
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pending-verification This issue is pending verification and/or reproduction

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@kamilrakoczy
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Version

Yosys 0.47+22 (git sha1 cef87cc, g++ 12.2.0-14 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

Process SystemVerilog code (a.sv):

module foo #(parameter [1:0] a) (output [1:0] o);
	assign o = a;
endmodule

module top(output [1:0] o);
	foo #(2'b0x) foo(o);
endmodule

with following commands:

read_verilog -sv a.sv
setundef -zero -params
write_json out.json

Expected Behavior

File out.json should contain entry: "parameters": { "$1": "00" } responsible for foo's a parameter.

Actual Behavior

File out.json contains entry: "parameters": { "$1": "0x" } responsible for foo's a parameter.

@kamilrakoczy kamilrakoczy added the pending-verification This issue is pending verification and/or reproduction label Nov 12, 2024
@kamilrakoczy kamilrakoczy linked a pull request Nov 12, 2024 that will close this issue
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