Fix: handle VCD variable references with and without whitespace #4620
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mmicko
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Co-authored-by: Miodrag Milanović <[email protected]> Co-authored-by: Roland Coeurjoly <[email protected]>
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Rebased on main. Changed |
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What are the reasons/motivation for this change?
Fixes #4617.
Explain how this is achieved.
We detect if a variable reference in the VCD file contains a space between the signal name and the bit range. If no space is detected, the bit or part-select is parsed and removed from the signal name.
If applicable, please suggest to reviewers how they can test the change.
In addition to the added test case, I processed the neorv32 design with its GHDL-generated VCD file, and the
simpass did not report any issues. It might be helpful to test with other real-world examples, but I believe the current testing is sufficient to verify the fix