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read_verilog <<EOT
(* blackbox *)
module passthrough(
input wire in, // Input signal
output wire out // Output signal
);
// Assign the output to be the same as the input
assign out = in;
endmodule
EOT
cutpoint =*
I get:
Executing CUTPOINT pass.
Note that if the module is not a blackbox:
read_verilog <<EOT
module passthrough(
input wire in, // Input signal
output wire out // Output signal
);
// Assign the output to be the same as the input
assign out = in;
endmodule
EOT
cutpoint =*
Executing CUTPOINT pass.
Making all outputs of module passthrough cut points, removing module contents.
Expected Behavior
Executing CUTPOINT pass.
Making all outputs of module passthrough cut points, removing module contents.
Actual Behavior
Executing CUTPOINT pass.
The text was updated successfully, but these errors were encountered:
Version
Yosys 0.44+39 (git sha1 32d770d64, g++ 13.2.0 -Og -fPIC)
On which OS did this happen?
Linux
Reproduction Steps
I get:
Note that if the module is not a
blackbox
:Expected Behavior
Actual Behavior
The text was updated successfully, but these errors were encountered: