@@ -31,6 +31,24 @@ PRIVATE_NAMESPACE_BEGIN
3131
3232using RTLIL::id2cstr;
3333
34+ struct CleanerPool : SigPool
35+ {
36+ bool check_all_def (const RTLIL::SigSpec &sig) const
37+ {
38+ for (auto &bit : sig) {
39+ if (bit.wire != NULL && bits.count (bit) == 0 )
40+ return false ;
41+ if (bit.wire == NULL && bit.data == RTLIL::State::Sx)
42+ return false ;
43+ }
44+ return true ;
45+ }
46+ bool check_def (const RTLIL::SigBit &bit) const
47+ {
48+ return (bit.wire != NULL && bits.count (bit)) || (bit.wire == NULL && bit.data != RTLIL::State::Sx);
49+ }
50+ };
51+
3452struct keep_cache_t
3553{
3654 Design *design;
@@ -356,7 +374,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
356374 // used signals pre-sigmapped
357375 SigPool raw_used_signals;
358376 // used signals sigmapped, ignoring drivers (we keep track of this to set `unused_bits`)
359- SigPool used_signals_nodrivers;
377+ CleanerPool used_signals_nodrivers;
360378
361379 // gather the usage information for cells
362380 for (auto &it : module ->cells_ ) {
@@ -472,14 +490,14 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
472490 module ->connect (new_conn);
473491 }
474492
475- if (!used_signals_nodrivers.check_all (s2)) {
493+ if (!used_signals_nodrivers.check_all_def (s2)) {
476494 std::string unused_bits;
477495 for (int i = 0 ; i < GetSize (s2); i++) {
478- if (s2[i].wire == NULL )
479- continue ;
480- if (!used_signals_nodrivers.check (s2[i])) {
496+ if (( s2[i].wire == NULL ) && (s2[i]. data != RTLIL::State::Sx) )
497+ continue ;
498+ if (!used_signals_nodrivers.check_def (s2[i])) {
481499 if (!unused_bits.empty ())
482- unused_bits += " " ;
500+ unused_bits += " " ;
483501 unused_bits += stringf (" %d" , i);
484502 }
485503 }
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