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The XTheadFMemIdx instruction that perform a zero-extension of the index
register (those with a `u` in the name) are identical to the
sign-extension counterparts on RV32. Therefore, it does not make sense
to offer both for RV32.
Further, the table lists the 8-byte loads/stores as compatible with the
`F` extensions. However, 8-byte loads won't fit into single-precision
floating-point register. And 8-byte stores can't be performed from a
single-precision floating-point register. Instead of defining truncation
and extension for these cases, let's make the instructions only
available for those cases where they make sense.
FixesXUANTIE-RV#49.
Signed-off-by: Christoph Müllner <[email protected]>
We should drop th.flurw from RV32, just like we did with th.lur* and th.sur* in the referenced change for the XTheadMemidx extension. The whole table in the XTheadFMemIdx seems to be incorrect and deserves a rework.
Afaik, there is no implementation of XTheadFMemIdx in any of T-Head's RV32 cores. The E902 and the E906 only implement XTheadCmo and XTheadSync. So we can safely edit the spec (and all implementations that follow) without worrying too much.
The xtheadfmemidx doc says "All instructions are available for RV32 and RV64". But th.flurw seems identical to th.flrw on RV32.
I found this patch that removed some of the "u" instructions from RV32 for xtheadmemidx. 5d38f4f
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