Rounding Average instructions #126
Conversation
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Added examples of applications. @arunetm, @AndrewScheidecker, @sunfishcode, @dtig, @penzn, @tlively, @abrown PTAL |
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I don't have much experience with codecs but the example applications make a good case for including this instruction. Thanks for making the x86 encodings explicit--they make sense to me. |
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I'm in favor of adding these operations to the proposal. These are well supported on multiple relevant platforms, and emulating them is expensive. The examples listed by @Maratyszcza are compelling use cases. Are there any objections to adding these to the proposal? Adding a poll here for responses. In favor of including Rounding Average operations in the current proposal, please respond with 👍 |
Summary: These instructions were added to the spec proposal in WebAssembly/simd#126. Their semantics are equivalent to `(a + b + 1) / 2`. The opcode for the experimental i32x4.dot_i16x8_s is also bumped due to a collision with the i8x16.avgr_u opcode. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71628
As specified in WebAssembly/simd#126.
As specified in WebAssembly/simd#126.
3 participants
Introduction
Rounding Average of two integer inputs, defined as
avg(a, b) := (a + b + 1) >> 1, is a common operation in fixed-point numerical algorithms, such as video- and audio-codecs, and image filtering. Direct implementation of Rounding Average in SIMD instruction sets following the formula(a + b + 1) >> 1is tricky, because while the suma + b + 1can overflow the datatype of inputs, the final result always fits into the same datatype. To avoid the expensive work-around of computinga + b + 1in higher precision (e.g. extending inputs from 8-bit elements to 16-bit elements for the computation), all common SIMD instruction sets provide some forms of Rounding Average instructions.This PR introduce two new WebAssembly instructions for Rounding Average operations,
i8x16.avgr_uandi16x8.avgr_u, which operate on vectors of unsigned 8-bit and unsigned 16-bit integers accordingly. These instructions match the universally supported across x86, ARM, and POWER forms of the Rounding Average operation.[October 31 update] Applications
Below are examples of optimized libraries using close equivalents of the proposed
i8x16.avgr_uandi16x8.avgr_uinstructions:Mapping to Common Instruction Sets
This section illustrates how the new WebAssembly instructions can be lowered on common instruction sets. However, these patterns are provided only for convenience, compliant WebAssembly implementations do not have to follow the same code generation patterns.
x86/x86-64 processors with AVX instruction set
y = i8x16.avgr_u(a, b)is lowered toVPAVGB xmm_y, xmm_a, xmm_by = i16x8.avgr_u(a, b)is lowered toVPAVGW xmm_y, xmm_a, xmm_bx86/x86-64 processors with SSE2 instruction set
a = i8x16.avgr_u(a, b)is lowered toPAVGB xmm_a, xmm_by = i8x16.avgr_u(a, b)is lowered toMOVDQA xmm_y, xmm_a + PAVGB xmm_y, xmm_ba = i16x8.avgr_u(a, b)is lowered toPAVGW xmm_a, xmm_by = i16x8.avgr_u(a, b)is lowered toMOVDQA xmm_y, xmm_a + PAVGW xmm_y, xmm_bARM64 processors
y = i8x16.avgr_u(a, b)is lowered toURHADD Vy.16B, Va.16B, Vb.16By = i16x8.avgr_u(a, b)is lowered toURHADD Vy.8H, Va.8H, Vb.8HARMv7 processors with NEON instruction set
y = i8x16.avgr_u(a, b)is lowered toVRHADD.U8 Qy, Qa, Qby = i16x8.avgr_u(a, b)is lowered toVRHADD.U16 Qy, Qa, QbPOWER processors with VMX (Altivec) instruction set
y = i8x16.avgr_u(a, b)is lowered toVAVGUB VRy, VRa, VRby = i16x8.avgr_u(a, b)is lowered toVAVGUH VRy, VRa, VRbMIPS processors with MSA instruction set
y = i8x16.avgr_u(a, b)is lowered toAVER_U.B Wy, Wa, Wby = i16x8.avgr_u(a, b)is lowered toAVER_U.H Wy, Wa, Wb