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[spectext] Rename integer widen instructions to integer extend
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Changes to interpreter will come in a follow-up patch.

Fixed #467.
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@ngzhian
ngzhian committed Feb 23, 2021
1 parent 958c09b commit 64b8775
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Showing 12 changed files with 132 additions and 132 deletions.
24 changes: 12 additions & 12 deletions document/core/appendix/gen-index-instructions.py
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Original file line number Diff line number Diff line change
Expand Up @@ -446,10 +446,10 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
Instruction(r'\I16X8.\BITMASK', r'\hex{FD}~~132', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
Instruction(r'\I16X8.\NARROW\K{\_i16x8\_s}', r'\hex{FD}~~133', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-simd-narrow'),
Instruction(r'\I16X8.\NARROW\K{\_i16x8\_u}', r'\hex{FD}~~134', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-simd-narrow'),
Instruction(r'\I16X8.\WIDEN\K{\_low\_i8x16\_s}', r'\hex{FD}~~135', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I16X8.\WIDEN\K{\_high\_i8x16\_s}', r'\hex{FD}~~136', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I16X8.\WIDEN\K{\_low\_i8x16\_u}', r'\hex{FD}~~137', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I16X8.\WIDEN\K{\_high\_i8x16\_u}', r'\hex{FD}~~138', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I16X8.\VEXTEND\K{\_low\_i8x16\_s}', r'\hex{FD}~~135', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I16X8.\VEXTEND\K{\_high\_i8x16\_s}', r'\hex{FD}~~136', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I16X8.\VEXTEND\K{\_low\_i8x16\_u}', r'\hex{FD}~~137', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I16X8.\VEXTEND\K{\_high\_i8x16\_u}', r'\hex{FD}~~138', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I16X8.\VSHL', r'\hex{FD}~~139', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'),
Instruction(r'\I16X8.\VSHR\K{\_s}', r'\hex{FD}~~140', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'),
Instruction(r'\I16X8.\VSHR\K{\_u}', r'\hex{FD}~~141', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'),
Expand All @@ -474,10 +474,10 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
Instruction(r'\I32X4.\VNEG', r'\hex{FD}~~161', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'),
Instruction(r'\I32X4.\ALLTRUE', r'\hex{FD}~~163', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'),
Instruction(r'\I32X4.\BITMASK', r'\hex{FD}~~164', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
Instruction(r'\I32X4.\WIDEN\K{\_low\_i16x8\_s}', r'\hex{FD}~~167', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I32X4.\WIDEN\K{\_high\_i16x8\_s}', r'\hex{FD}~~168', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I32X4.\WIDEN\K{\_low\_i16x8\_u}', r'\hex{FD}~~169', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I32X4.\WIDEN\K{\_high\_i16x8\_u}', r'\hex{FD}~~170', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_s}', r'\hex{FD}~~167', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_s}', r'\hex{FD}~~168', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_u}', r'\hex{FD}~~169', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_u}', r'\hex{FD}~~170', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I32X4.\VSHL', r'\hex{FD}~~171', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'),
Instruction(r'\I32X4.\VSHR\K{\_s}', r'\hex{FD}~~172', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'),
Instruction(r'\I32X4.\VSHR\K{\_u}', r'\hex{FD}~~173', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'),
Expand All @@ -495,10 +495,10 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
Instruction(r'\I64X2.\VABS', r'\hex{FD}~~162', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'),
Instruction(r'\I64X2.\VNEG', r'\hex{FD}~~193', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'),
Instruction(r'\I64X2.\BITMASK', r'\hex{FD}~~196', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
Instruction(r'\I64X2.\WIDEN\K{\_low\_i32x4\_s}', r'\hex{FD}~~199', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I64X2.\WIDEN\K{\_high\_i32x4\_s}', r'\hex{FD}~~200', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I64X2.\WIDEN\K{\_low\_i32x4\_u}', r'\hex{FD}~~201', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I64X2.\WIDEN\K{\_high\_i32x4\_u}', r'\hex{FD}~~202', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
Instruction(r'\I64X2.\VEXTEND\K{\_low\_i32x4\_s}', r'\hex{FD}~~199', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I64X2.\VEXTEND\K{\_high\_i32x4\_s}', r'\hex{FD}~~200', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I64X2.\VEXTEND\K{\_low\_i32x4\_u}', r'\hex{FD}~~201', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I64X2.\VEXTEND\K{\_high\_i32x4\_u}', r'\hex{FD}~~202', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
Instruction(r'\I64X2.\VSHL', r'\hex{FD}~~203', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'),
Instruction(r'\I64X2.\VSHR\K{\_s}', r'\hex{FD}~~204', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'),
Instruction(r'\I64X2.\VSHR\K{\_u}', r'\hex{FD}~~205', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'),
Expand Down
24 changes: 12 additions & 12 deletions document/core/appendix/index-instructions.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -394,10 +394,10 @@ Instruction Binary Opcode Type
:math:`\I16X8.\BITMASK` :math:`\hex{FD}~~132` :math:`[\V128] \to [\I32]` :ref:`validation <valid-simd-bitmask>` :ref:`execution <exec-simd-bitmask>`
:math:`\I16X8.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~133` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-simd-narrow>`
:math:`\I16X8.\NARROW\K{\_i16x8\_u}` :math:`\hex{FD}~~134` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-simd-narrow>`
:math:`\I16X8.\WIDEN\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~135` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I16X8.\WIDEN\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~136` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I16X8.\WIDEN\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~137` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I16X8.\WIDEN\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~138` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~135` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~136` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~137` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~138` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I16X8.\VSHL` :math:`\hex{FD}~~139` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishl>`
:math:`\I16X8.\VSHR\K{\_s}` :math:`\hex{FD}~~140` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_s>`
:math:`\I16X8.\VSHR\K{\_u}` :math:`\hex{FD}~~141` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_u>`
Expand All @@ -422,10 +422,10 @@ Instruction Binary Opcode Type
:math:`\I32X4.\VNEG` :math:`\hex{FD}~~161` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-ineg>`
:math:`\I32X4.\ALLTRUE` :math:`\hex{FD}~~163` :math:`[\V128] \to [\I32]` :ref:`validation <valid-vitestop>` :ref:`execution <exec-vitestop>`
:math:`\I32X4.\BITMASK` :math:`\hex{FD}~~164` :math:`[\V128] \to [\I32]` :ref:`validation <valid-simd-bitmask>` :ref:`execution <exec-simd-bitmask>`
:math:`\I32X4.\WIDEN\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~167` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I32X4.\WIDEN\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~168` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I32X4.\WIDEN\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~169` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I32X4.\WIDEN\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~170` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~167` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~168` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~169` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~170` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I32X4.\VSHL` :math:`\hex{FD}~~171` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishl>`
:math:`\I32X4.\VSHR\K{\_s}` :math:`\hex{FD}~~172` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_s>`
:math:`\I32X4.\VSHR\K{\_u}` :math:`\hex{FD}~~173` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_u>`
Expand All @@ -443,10 +443,10 @@ Instruction Binary Opcode Type
:math:`\I64X2.\VABS` :math:`\hex{FD}~~162` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-iabs>`
:math:`\I64X2.\VNEG` :math:`\hex{FD}~~193` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-ineg>`
:math:`\I64X2.\BITMASK` :math:`\hex{FD}~~196` :math:`[\V128] \to [\I32]` :ref:`validation <valid-simd-bitmask>` :ref:`execution <exec-simd-bitmask>`
:math:`\I64X2.\WIDEN\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~199` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I64X2.\WIDEN\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~200` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I64X2.\WIDEN\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~201` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I64X2.\WIDEN\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~202` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~199` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~200` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~201` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~202` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
:math:`\I64X2.\VSHL` :math:`\hex{FD}~~203` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishl>`
:math:`\I64X2.\VSHR\K{\_s}` :math:`\hex{FD}~~204` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_s>`
:math:`\I64X2.\VSHR\K{\_u}` :math:`\hex{FD}~~205` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_u>`
Expand Down
24 changes: 12 additions & 12 deletions document/core/binary/instructions.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -640,10 +640,10 @@ All other SIMD instructions are plain opcodes without any immediates.
\hex{FD}~~132{:}\Bu32 &\Rightarrow& \I16X8.\BITMASK \\ &&|&
\hex{FD}~~133{:}\Bu32 &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_s} \\ &&|&
\hex{FD}~~134{:}\Bu32 &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_u} \\ &&|&
\hex{FD}~~135{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_low\_i8x16\_s} \\ &&|&
\hex{FD}~~136{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_high\_i8x16\_s} \\ &&|&
\hex{FD}~~137{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_low\_i8x16\_u} \\ &&|&
\hex{FD}~~138{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_high\_i8x16\_u} \\ &&|&
\hex{FD}~~135{:}\Bu32 &\Rightarrow& \I16X8.\VEXTEND\K{\_low\_i8x16\_s} \\ &&|&
\hex{FD}~~136{:}\Bu32 &\Rightarrow& \I16X8.\VEXTEND\K{\_high\_i8x16\_s} \\ &&|&
\hex{FD}~~137{:}\Bu32 &\Rightarrow& \I16X8.\VEXTEND\K{\_low\_i8x16\_u} \\ &&|&
\hex{FD}~~138{:}\Bu32 &\Rightarrow& \I16X8.\VEXTEND\K{\_high\_i8x16\_u} \\ &&|&
\hex{FD}~~139{:}\Bu32 &\Rightarrow& \I16X8.\VSHL \\ &&|&
\hex{FD}~~140{:}\Bu32 &\Rightarrow& \I16X8.\VSHR\K{\_s} \\ &&|&
\hex{FD}~~141{:}\Bu32 &\Rightarrow& \I16X8.\VSHR\K{\_u} \\ &&|&
Expand Down Expand Up @@ -673,10 +673,10 @@ All other SIMD instructions are plain opcodes without any immediates.
\hex{FD}~~161{:}\Bu32 &\Rightarrow& \I32X4.\VNEG \\ &&|&
\hex{FD}~~163{:}\Bu32 &\Rightarrow& \I32X4.\ALLTRUE \\ &&|&
\hex{FD}~~164{:}\Bu32 &\Rightarrow& \I32X4.\BITMASK \\ &&|&
\hex{FD}~~167{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_s} \\ &&|&
\hex{FD}~~168{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_s} \\ &&|&
\hex{FD}~~169{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_u} \\ &&|&
\hex{FD}~~170{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_u} \\ &&|&
\hex{FD}~~167{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_s} \\ &&|&
\hex{FD}~~168{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_s} \\ &&|&
\hex{FD}~~169{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_u} \\ &&|&
\hex{FD}~~170{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_u} \\ &&|&
\hex{FD}~~171{:}\Bu32 &\Rightarrow& \I32X4.\VSHL \\ &&|&
\hex{FD}~~172{:}\Bu32 &\Rightarrow& \I32X4.\VSHR\K{\_s} \\ &&|&
\hex{FD}~~173{:}\Bu32 &\Rightarrow& \I32X4.\VSHR\K{\_u} \\ &&|&
Expand All @@ -699,10 +699,10 @@ All other SIMD instructions are plain opcodes without any immediates.
\hex{FD}~~162{:}\Bu32 &\Rightarrow& \I64X2.\VABS \\ &&|&
\hex{FD}~~193{:}\Bu32 &\Rightarrow& \I64X2.\VNEG \\ &&|&
\hex{FD}~~196{:}\Bu32 &\Rightarrow& \I64X2.\BITMASK \\ &&|&
\hex{FD}~~199{:}\Bu32 &\Rightarrow& \I64X2.\WIDEN\K{\_low\_i32x4\_s} \\ &&|&
\hex{FD}~~200{:}\Bu32 &\Rightarrow& \I64X2.\WIDEN\K{\_high\_i32x4\_s} \\ &&|&
\hex{FD}~~201{:}\Bu32 &\Rightarrow& \I64X2.\WIDEN\K{\_low\_i32x4\_u} \\ &&|&
\hex{FD}~~202{:}\Bu32 &\Rightarrow& \I64X2.\WIDEN\K{\_high\_i32x4\_u} \\ &&|&
\hex{FD}~~199{:}\Bu32 &\Rightarrow& \I64X2.\VEXTEND\K{\_low\_i32x4\_s} \\ &&|&
\hex{FD}~~200{:}\Bu32 &\Rightarrow& \I64X2.\VEXTEND\K{\_high\_i32x4\_s} \\ &&|&
\hex{FD}~~201{:}\Bu32 &\Rightarrow& \I64X2.\VEXTEND\K{\_low\_i32x4\_u} \\ &&|&
\hex{FD}~~202{:}\Bu32 &\Rightarrow& \I64X2.\VEXTEND\K{\_high\_i32x4\_u} \\ &&|&
\hex{FD}~~203{:}\Bu32 &\Rightarrow& \I64X2.\VSHL \\ &&|&
\hex{FD}~~204{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_s} \\ &&|&
\hex{FD}~~205{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_u} \\ &&|&
Expand Down
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