VUnit · eine · Nov 14, 2019 · Nov 2, 2019 · Nov 3, 2019 · Nov 13, 2019
diff --git a/docs/cli.rst b/docs/cli.rst
@@ -2,13 +2,13 @@
 
 Command Line Interface
 ======================
-A :class:`VUnit <vunit.ui.vunit.VUnit>` object can be created from command
+A :class:`VUnit <vunit.ui.VUnit>` object can be created from command
 line arguments by using the :meth:`from_argv
-<vunit.ui.vunit.VUnit.from_argv>` method effectively creating a custom
+<vunit.ui.VUnit.from_argv>` method effectively creating a custom
 command line tool for running tests in the user project.  Source files
 and libraries are added to the project by using methods on the VUnit
 object. The configuration is followed by a call to the :meth:`main
-<vunit.ui.vunit.VUnit.main>` method which will execute the function
+<vunit.ui.VUnit.main>` method which will execute the function
 specified by the command line arguments and exit the script. The added
 source files are automatically scanned for test cases.
 

diff --git a/docs/installing.rst b/docs/installing.rst
@@ -27,7 +27,7 @@ Start by cloning our `GIT repository on GitHub <https://github.com/vunit/vunit/>
 
 The ``--recursive`` option initializes `OSVVM <https://github.com/JimLewis/OSVVM>`__ which is included as a submodule in the VUnit repository.
 
-To be able to import :class:`VUnit <vunit.ui.vunit.VUnit>` in your ``run.py`` script
+To be able to import :class:`VUnit <vunit.ui.VUnit>` in your ``run.py`` script
 you need to make it visible to Python or else the following error
 occurs.
 

diff --git a/docs/py/ui.rst b/docs/py/ui.rst
@@ -3,7 +3,7 @@
 Python Interface
 ================
 The Python interface of VUnit is exposed through the :class:`VUnit
-class <vunit.ui.vunit.VUnit>` that can be imported directly. See the
+class <vunit.ui.VUnit>` that can be imported directly. See the
 :ref:`User Guide <user_guide>` for a quick introduction. The
 following list provides detailed references of the Python API and
 about how to set compilation and simulation options.

diff --git a/docs/py/vunit.rst b/docs/py/vunit.rst
@@ -1,7 +1,7 @@
-vunit.ui.vunit
+vunit.ui
 ==============
 
-.. autoclass:: vunit.ui.vunit.VUnit()
+.. autoclass:: vunit.ui.VUnit()
    :exclude-members: add_preprocessor,
       add_builtins
 

diff --git a/setup.py b/setup.py
@@ -40,14 +40,16 @@ def find_all_files(directory, endings=None):
     name="vunit_hdl",
     version=version(),
     packages=[
+        "tests",
+        "tests.lint",
+        "tests.unit",
+        "tests.acceptance",
         "vunit",
         "vunit.com",
         "vunit.parsing",
         "vunit.parsing.verilog",
+        "vunit.sim_if",
         "vunit.test",
-        "vunit.test.lint",
-        "vunit.test.unit",
-        "vunit.test.acceptance",
         "vunit.ui",
         "vunit.vivado",
     ],

diff --git a/vunit/test/acceptance/__init__.py → tests/__init__.py b/vunit/test/acceptance/__init__.py → tests/__init__.py
diff --git a/vunit/test/lint/__init__.py → tests/acceptance/__init__.py b/vunit/test/lint/__init__.py → tests/acceptance/__init__.py
diff --git a/...ce/artificial/verilog/other_file_tests.sv → ...ce/artificial/verilog/other_file_tests.sv b/...ce/artificial/verilog/other_file_tests.sv → ...ce/artificial/verilog/other_file_tests.sv
diff --git a/...test/acceptance/artificial/verilog/run.py → tests/acceptance/artificial/verilog/run.py b/...test/acceptance/artificial/verilog/run.py → tests/acceptance/artificial/verilog/run.py
diff --git a/...ilog/tb_fail_on_fatal_and_early_finish.sv → ...ilog/tb_fail_on_fatal_and_early_finish.sv b/...ilog/tb_fail_on_fatal_and_early_finish.sv → ...ilog/tb_fail_on_fatal_and_early_finish.sv
diff --git a/.../artificial/verilog/tb_fail_on_warning.sv → .../artificial/verilog/tb_fail_on_warning.sv b/.../artificial/verilog/tb_fail_on_warning.sv → .../artificial/verilog/tb_fail_on_warning.sv
diff --git a/...ance/artificial/verilog/tb_magic_paths.sv → ...ance/artificial/verilog/tb_magic_paths.sv b/...ance/artificial/verilog/tb_magic_paths.sv → ...ance/artificial/verilog/tb_magic_paths.sv
diff --git a/...artificial/verilog/tb_other_file_tests.sv → ...artificial/verilog/tb_other_file_tests.sv b/...artificial/verilog/tb_other_file_tests.sv → ...artificial/verilog/tb_other_file_tests.sv
diff --git a/...rtificial/verilog/tb_same_sim_all_pass.sv → ...rtificial/verilog/tb_same_sim_all_pass.sv b/...rtificial/verilog/tb_same_sim_all_pass.sv → ...rtificial/verilog/tb_same_sim_all_pass.sv
diff --git a/...tificial/verilog/tb_same_sim_some_fail.sv → ...tificial/verilog/tb_same_sim_some_fail.sv b/...tificial/verilog/tb_same_sim_some_fail.sv → ...tificial/verilog/tb_same_sim_some_fail.sv
diff --git a/...ance/artificial/verilog/tb_with_define.sv → ...ance/artificial/verilog/tb_with_define.sv b/...ance/artificial/verilog/tb_with_define.sv → ...ance/artificial/verilog/tb_with_define.sv
diff --git a/...icial/verilog/tb_with_parameter_config.sv → ...icial/verilog/tb_with_parameter_config.sv b/...icial/verilog/tb_with_parameter_config.sv → ...icial/verilog/tb_with_parameter_config.sv
diff --git a/...ance/artificial/verilog/tb_with_runner.sv → ...ance/artificial/verilog/tb_with_runner.sv b/...ance/artificial/verilog/tb_with_runner.sv → ...ance/artificial/verilog/tb_with_runner.sv
diff --git a/...cceptance/artificial/vhdl/bool_driver.vhd → ...cceptance/artificial/vhdl/bool_driver.vhd b/...cceptance/artificial/vhdl/bool_driver.vhd → ...cceptance/artificial/vhdl/bool_driver.vhd
diff --git a/...ance/artificial/vhdl/other_file_tests.vhd → ...ance/artificial/vhdl/other_file_tests.vhd b/...ance/artificial/vhdl/other_file_tests.vhd → ...ance/artificial/vhdl/other_file_tests.vhd
diff --git a/vunit/test/acceptance/artificial/vhdl/run.py → tests/acceptance/artificial/vhdl/run.py b/vunit/test/acceptance/artificial/vhdl/run.py → tests/acceptance/artificial/vhdl/run.py
diff --git a/.../artificial/vhdl/tb_assert_stop_level.vhd → .../artificial/vhdl/tb_assert_stop_level.vhd b/.../artificial/vhdl/tb_assert_stop_level.vhd → .../artificial/vhdl/tb_assert_stop_level.vhd
diff --git a/...ceptance/artificial/vhdl/tb_elab_fail.vhd → ...ceptance/artificial/vhdl/tb_elab_fail.vhd b/...ceptance/artificial/vhdl/tb_elab_fail.vhd → ...ceptance/artificial/vhdl/tb_elab_fail.vhd
diff --git a/...st/acceptance/artificial/vhdl/tb_fail.vhd → tests/acceptance/artificial/vhdl/tb_fail.vhd b/...st/acceptance/artificial/vhdl/tb_fail.vhd → tests/acceptance/artificial/vhdl/tb_fail.vhd
diff --git a/...ce/artificial/vhdl/tb_fail_on_warning.vhd → ...ce/artificial/vhdl/tb_fail_on_warning.vhd b/...ce/artificial/vhdl/tb_fail_on_warning.vhd → ...ce/artificial/vhdl/tb_fail_on_warning.vhd
diff --git a/...tance/artificial/vhdl/tb_ieee_warning.vhd → ...tance/artificial/vhdl/tb_ieee_warning.vhd b/...tance/artificial/vhdl/tb_ieee_warning.vhd → ...tance/artificial/vhdl/tb_ieee_warning.vhd
diff --git a/...ce/artificial/vhdl/tb_infinite_events.vhd → ...ce/artificial/vhdl/tb_infinite_events.vhd b/...ce/artificial/vhdl/tb_infinite_events.vhd → ...ce/artificial/vhdl/tb_infinite_events.vhd
diff --git a/...ptance/artificial/vhdl/tb_magic_paths.vhd → ...ptance/artificial/vhdl/tb_magic_paths.vhd b/...ptance/artificial/vhdl/tb_magic_paths.vhd → ...ptance/artificial/vhdl/tb_magic_paths.vhd
@@ -23,8 +23,8 @@ begin
     end procedure;
   begin
     test_runner_setup(runner, runner_cfg);
-    check_has_suffix(tb_path, "/vunit/test/acceptance/artificial/vhdl/");
-    check_has_suffix(vunit_lib.run_pkg.tb_path(runner_cfg), "/vunit/test/acceptance/artificial/vhdl/");
+    check_has_suffix(tb_path, "/tests/acceptance/artificial/vhdl/");
+    check_has_suffix(vunit_lib.run_pkg.tb_path(runner_cfg), "/tests/acceptance/artificial/vhdl/");
     test_runner_cleanup(runner);
     wait;
   end process;

diff --git a/...ificial/vhdl/tb_no_fail_after_cleanup.vhd → ...ificial/vhdl/tb_no_fail_after_cleanup.vhd b/...ificial/vhdl/tb_no_fail_after_cleanup.vhd → ...ificial/vhdl/tb_no_fail_after_cleanup.vhd
diff --git a/...artificial/vhdl/tb_no_fail_on_warning.vhd → ...artificial/vhdl/tb_no_fail_on_warning.vhd b/...artificial/vhdl/tb_no_fail_on_warning.vhd → ...artificial/vhdl/tb_no_fail_on_warning.vhd
diff --git a/...rtificial/vhdl/tb_no_generic_override.vhd → ...rtificial/vhdl/tb_no_generic_override.vhd b/...rtificial/vhdl/tb_no_generic_override.vhd → ...rtificial/vhdl/tb_no_generic_override.vhd
diff --git a/...e/artificial/vhdl/tb_other_file_tests.vhd → ...e/artificial/vhdl/tb_other_file_tests.vhd b/...e/artificial/vhdl/tb_other_file_tests.vhd → ...e/artificial/vhdl/tb_other_file_tests.vhd
diff --git a/...st/acceptance/artificial/vhdl/tb_pass.vhd → tests/acceptance/artificial/vhdl/tb_pass.vhd b/...st/acceptance/artificial/vhdl/tb_pass.vhd → tests/acceptance/artificial/vhdl/tb_pass.vhd
diff --git a/.../artificial/vhdl/tb_same_sim_all_pass.vhd → .../artificial/vhdl/tb_same_sim_all_pass.vhd b/.../artificial/vhdl/tb_same_sim_all_pass.vhd → .../artificial/vhdl/tb_same_sim_all_pass.vhd
diff --git a/...artificial/vhdl/tb_same_sim_some_fail.vhd → ...artificial/vhdl/tb_same_sim_some_fail.vhd b/...artificial/vhdl/tb_same_sim_some_fail.vhd → ...artificial/vhdl/tb_same_sim_some_fail.vhd
diff --git a/...ptance/artificial/vhdl/tb_set_generic.vhd → ...ptance/artificial/vhdl/tb_set_generic.vhd b/...ptance/artificial/vhdl/tb_set_generic.vhd → ...ptance/artificial/vhdl/tb_set_generic.vhd
diff --git a/...ptance/artificial/vhdl/tb_with_checks.vhd → ...ptance/artificial/vhdl/tb_with_checks.vhd b/...ptance/artificial/vhdl/tb_with_checks.vhd → ...ptance/artificial/vhdl/tb_with_checks.vhd
diff --git a/...rtificial/vhdl/tb_with_generic_config.vhd → ...rtificial/vhdl/tb_with_generic_config.vhd b/...rtificial/vhdl/tb_with_generic_config.vhd → ...rtificial/vhdl/tb_with_generic_config.vhd
diff --git a/...e/artificial/vhdl/tb_with_vhdl_runner.vhd → ...e/artificial/vhdl/tb_with_vhdl_runner.vhd b/...e/artificial/vhdl/tb_with_vhdl_runner.vhd → ...e/artificial/vhdl/tb_with_vhdl_runner.vhd
diff --git a/vunit/test/acceptance/dependencies/pkg.vhd → tests/acceptance/dependencies/pkg.vhd b/vunit/test/acceptance/dependencies/pkg.vhd → tests/acceptance/dependencies/pkg.vhd
diff --git a/...est/acceptance/dependencies/pkg_body1.vhd → tests/acceptance/dependencies/pkg_body1.vhd b/...est/acceptance/dependencies/pkg_body1.vhd → tests/acceptance/dependencies/pkg_body1.vhd
diff --git a/...est/acceptance/dependencies/pkg_body2.vhd → tests/acceptance/dependencies/pkg_body2.vhd b/...est/acceptance/dependencies/pkg_body2.vhd → tests/acceptance/dependencies/pkg_body2.vhd
diff --git a/...t/test/acceptance/dependencies/tb_pkg.vhd → tests/acceptance/dependencies/tb_pkg.vhd b/...t/test/acceptance/dependencies/tb_pkg.vhd → tests/acceptance/dependencies/tb_pkg.vhd
diff --git a/vunit/test/acceptance/test_artificial.py → tests/acceptance/test_artificial.py b/vunit/test/acceptance/test_artificial.py → tests/acceptance/test_artificial.py
@@ -8,13 +8,13 @@
 Acceptance test of VUnit end to end functionality
 """
 
-
 import unittest
 from os.path import join, dirname
 from os import environ
 from subprocess import call
 import sys
-from vunit.test.common import has_simulator, check_report, simulator_is
+from tests.common import check_report
+from vunit.sim_if.common import has_simulator, simulator_is
 
 
 @unittest.skipUnless(has_simulator(), "Requires simulator")

diff --git a/vunit/test/acceptance/test_dependencies.py → tests/acceptance/test_dependencies.py b/vunit/test/acceptance/test_dependencies.py → tests/acceptance/test_dependencies.py
diff --git a/...t/acceptance/test_external_run_scripts.py → ...s/acceptance/test_external_run_scripts.py b/...t/acceptance/test_external_run_scripts.py → ...s/acceptance/test_external_run_scripts.py
@@ -8,15 +8,15 @@
 Verify that all external run scripts work correctly
 """
 
-
 import unittest
 from os import environ
 from os.path import join, dirname
 from subprocess import call
 import sys
+from tests.common import check_report
 from vunit import ROOT
 from vunit.builtins import VHDL_PATH
-from vunit.test.common import has_simulator, check_report, simulator_is, simulator_check
+from vunit.sim_if.common import has_simulator, simulator_is, simulator_check
 
 
 def simulator_supports_verilog():

diff --git a/vunit/test/common.py → tests/common.py b/vunit/test/common.py → tests/common.py
@@ -8,38 +8,12 @@
 Common functions re-used between test cases
 """
 
-
 from xml.etree import ElementTree
 import contextlib
 import functools
 import os
 import shutil
 import random
-from vunit.simulator_factory import SIMULATOR_FACTORY
-
-
-def has_simulator():
-    return SIMULATOR_FACTORY.has_simulator
-
-
-def simulator_is(*names):
-    """
-    Check that current simulator is any of names
-    """
-    supported_names = [sim.name for sim in SIMULATOR_FACTORY.supported_simulators()]
-    for name in names:
-        assert name in supported_names
-    return SIMULATOR_FACTORY.select_simulator().name in names
-
-
-def simulator_check(func):
-    """
-    Check some method of the selected simulator
-    """
-    simif = SIMULATOR_FACTORY.select_simulator()
-    if simif is None:
-        return False
-    return func(simif)
 
 
 def check_report(report_file, tests=None):

diff --git a/vunit/test/unit/__init__.py → tests/lint/__init__.py b/vunit/test/unit/__init__.py → tests/lint/__init__.py
diff --git a/vunit/test/lint/pylintrc → tests/lint/pylintrc b/vunit/test/lint/pylintrc → tests/lint/pylintrc
diff --git a/vunit/test/lint/test_license.py → tests/lint/test_license.py b/vunit/test/lint/test_license.py → tests/lint/test_license.py
diff --git a/vunit/test/lint/test_pycodestyle.py → tests/lint/test_pycodestyle.py b/vunit/test/lint/test_pycodestyle.py → tests/lint/test_pycodestyle.py
diff --git a/vunit/test/lint/test_pylint.py → tests/lint/test_pylint.py b/vunit/test/lint/test_pylint.py → tests/lint/test_pylint.py
@@ -13,7 +13,7 @@
 from subprocess import check_call
 from os.path import join, dirname
 import sys
-from vunit.test.lint.test_pycodestyle import get_files_and_folders
+from tests.lint.test_pycodestyle import get_files_and_folders
 
 
 class TestPylint(unittest.TestCase):

diff --git a/vunit/test/lint/test_readme.py → tests/lint/test_readme.py b/vunit/test/lint/test_readme.py → tests/lint/test_readme.py
diff --git a/vunit/test/mock_2or3.py → tests/mock_2or3.py b/vunit/test/mock_2or3.py → tests/mock_2or3.py
diff --git a/tests/unit/__init__.py b/tests/unit/__init__.py
@@ -0,0 +1,5 @@
+# This Source Code Form is subject to the terms of the Mozilla Public
+# License, v. 2.0. If a copy of the MPL was not distributed with this file,
+# You can obtain one at http://mozilla.org/MPL/2.0/.
+#
+# Copyright (c) 2014-2019, Lars Asplund [email protected]
diff --git a/vunit/test/unit/non_utf8_printer.py → tests/unit/non_utf8_printer.py b/vunit/test/unit/non_utf8_printer.py → tests/unit/non_utf8_printer.py
diff --git a/vunit/test/unit/test_activehdl_interface.py → tests/unit/test_activehdl_interface.py b/vunit/test/unit/test_activehdl_interface.py → tests/unit/test_activehdl_interface.py
@@ -13,8 +13,8 @@
 from os.path import join, dirname, exists
 import os
 from shutil import rmtree
-from vunit.activehdl_interface import ActiveHDLInterface
-from vunit.test.mock_2or3 import mock
+from tests.mock_2or3 import mock
+from vunit.sim_if.activehdl import ActiveHDLInterface
 from vunit.project import Project
 from vunit.ostools import renew_path, write_file
 from vunit.vhdl_standard import VHDL
@@ -25,10 +25,8 @@ class TestActiveHDLInterface(unittest.TestCase):
     Test the ActiveHDL interface
     """
 
-    @mock.patch(
-        "vunit.simulator_interface.check_output", autospec=True, return_value=""
-    )
-    @mock.patch("vunit.activehdl_interface.Process", autospec=True)
+    @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
+    @mock.patch("vunit.sim_if.activehdl.Process", autospec=True)
     def test_compile_project_vhdl_2008(self, process, check_output):
         simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
@@ -62,10 +60,8 @@ def test_compile_project_vhdl_2008(self, process, check_output):
             env=simif.get_env(),
         )
 
-    @mock.patch(
-        "vunit.simulator_interface.check_output", autospec=True, return_value=""
-    )
-    @mock.patch("vunit.activehdl_interface.Process", autospec=True)
+    @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
+    @mock.patch("vunit.sim_if.activehdl.Process", autospec=True)
     def test_compile_project_vhdl_2002(self, process, check_output):
         simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
@@ -99,10 +95,8 @@ def test_compile_project_vhdl_2002(self, process, check_output):
             env=simif.get_env(),
         )
 
-    @mock.patch(
-        "vunit.simulator_interface.check_output", autospec=True, return_value=""
-    )
-    @mock.patch("vunit.activehdl_interface.Process", autospec=True)
+    @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
+    @mock.patch("vunit.sim_if.activehdl.Process", autospec=True)
     def test_compile_project_vhdl_93(self, process, check_output):
         simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
@@ -136,10 +130,8 @@ def test_compile_project_vhdl_93(self, process, check_output):
             env=simif.get_env(),
         )
 
-    @mock.patch(
-        "vunit.simulator_interface.check_output", autospec=True, return_value=""
-    )
-    @mock.patch("vunit.activehdl_interface.Process", autospec=True)
+    @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
+    @mock.patch("vunit.sim_if.activehdl.Process", autospec=True)
     def test_compile_project_vhdl_extra_flags(self, process, check_output):
         simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
@@ -174,10 +166,8 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output):
             env=simif.get_env(),
         )
 
-    @mock.patch(
-        "vunit.simulator_interface.check_output", autospec=True, return_value=""
-    )
-    @mock.patch("vunit.activehdl_interface.Process", autospec=True)
+    @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
+    @mock.patch("vunit.sim_if.activehdl.Process", autospec=True)
     def test_compile_project_verilog(self, process, check_output):
         library_cfg = join(self.output_path, "library.cfg")
         simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path)
@@ -211,10 +201,8 @@ def test_compile_project_verilog(self, process, check_output):
             env=simif.get_env(),
         )
 
-    @mock.patch(
-        "vunit.simulator_interface.check_output", autospec=True, return_value=""
-    )
-    @mock.patch("vunit.activehdl_interface.Process", autospec=True)
+    @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
+    @mock.patch("vunit.sim_if.activehdl.Process", autospec=True)
     def test_compile_project_system_verilog(self, process, check_output):
         library_cfg = join(self.output_path, "library.cfg")
         simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path)
@@ -248,10 +236,8 @@ def test_compile_project_system_verilog(self, process, check_output):
             env=simif.get_env(),
         )
 
-    @mock.patch(
-        "vunit.simulator_interface.check_output", autospec=True, return_value=""
-    )
-    @mock.patch("vunit.activehdl_interface.Process", autospec=True)
+    @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
+    @mock.patch("vunit.sim_if.activehdl.Process", autospec=True)
     def test_compile_project_verilog_extra_flags(self, process, check_output):
         library_cfg = join(self.output_path, "library.cfg")
         simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path)
@@ -288,10 +274,8 @@ def test_compile_project_verilog_extra_flags(self, process, check_output):
             env=simif.get_env(),
         )
 
-    @mock.patch(
-        "vunit.simulator_interface.check_output", autospec=True, return_value=""
-    )
-    @mock.patch("vunit.activehdl_interface.Process", autospec=True)
+    @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
+    @mock.patch("vunit.sim_if.activehdl.Process", autospec=True)
     def test_compile_project_verilog_include(self, process, check_output):
         library_cfg = join(self.output_path, "library.cfg")
         simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path)
@@ -328,10 +312,8 @@ def test_compile_project_verilog_include(self, process, check_output):
             env=simif.get_env(),
         )
 
-    @mock.patch(
-        "vunit.simulator_interface.check_output", autospec=True, return_value=""
-    )
-    @mock.patch("vunit.activehdl_interface.Process", autospec=True)
+    @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
+    @mock.patch("vunit.sim_if.activehdl.Process", autospec=True)
     def test_compile_project_verilog_define(self, process, check_output):
         library_cfg = join(self.output_path, "library.cfg")
         simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path)

diff --git a/vunit/test/unit/test_builtins.py → tests/unit/test_builtins.py b/vunit/test/unit/test_builtins.py → tests/unit/test_builtins.py
@@ -9,7 +9,7 @@
 """
 
 import unittest
-from vunit.test.mock_2or3 import mock
+from tests.mock_2or3 import mock
 from vunit.builtins import BuiltinsAdder
 
 

diff --git a/vunit/test/unit/test_cds_file.py → tests/unit/test_cds_file.py b/vunit/test/unit/test_cds_file.py → tests/unit/test_cds_file.py
@@ -9,8 +9,8 @@
 """
 
 import unittest
-from vunit.test.mock_2or3 import mock
-from vunit.cds_file import CDSFile
+from tests.mock_2or3 import mock
+from vunit.sim_if.cds_file import CDSFile
 
 
 class TestCDSFile(unittest.TestCase):
@@ -90,15 +90,17 @@ def _create_cds_file(contents):
         """
         Create a CDSFile object with 'contents'
         """
-        with mock.patch("vunit.cds_file.read_file", autospec=True) as read_file:
+        with mock.patch("vunit.sim_if.cds_file.read_file", autospec=True) as read_file:
             read_file.return_value = contents
             return CDSFile.parse("file_name")
 
     def _check_written_as(self, cds, contents):
         """
         Check that the CDSFile object writes the 'contents to the file
         """
-        with mock.patch("vunit.cds_file.write_file", autospec=True) as write_file:
+        with mock.patch(
+            "vunit.sim_if.cds_file.write_file", autospec=True
+        ) as write_file:
             cds.write("filename")
             self.assertEqual(len(write_file.mock_calls), 1)
             args = write_file.mock_calls[0][1]

diff --git a/vunit/test/unit/test_check_preprocessor.py → tests/unit/test_check_preprocessor.py b/vunit/test/unit/test_check_preprocessor.py → tests/unit/test_check_preprocessor.py
diff --git a/vunit/test/unit/test_configuration.py → tests/unit/test_configuration.py b/vunit/test/unit/test_configuration.py → tests/unit/test_configuration.py
@@ -14,10 +14,10 @@
 import unittest
 import contextlib
 from os.path import join
+from tests.mock_2or3 import mock
+from tests.common import with_tempdir, create_tempdir
+from tests.unit.test_test_bench import Entity
 from vunit.configuration import Configuration, AttributeException
-from vunit.test.mock_2or3 import mock
-from vunit.test.common import with_tempdir, create_tempdir
-from vunit.test.unit.test_test_bench import Entity
 
 
 class TestConfiguration(unittest.TestCase):

diff --git a/vunit/test/unit/test_csv_logs.py → tests/unit/test_csv_logs.py b/vunit/test/unit/test_csv_logs.py → tests/unit/test_csv_logs.py
diff --git a/vunit/test/unit/test_database.py → tests/unit/test_database.py b/vunit/test/unit/test_database.py → tests/unit/test_database.py
@@ -10,8 +10,8 @@
 
 import unittest
 from os.path import join
+from tests.common import with_tempdir
 from vunit.database import DataBase, PickledDataBase
-from vunit.test.common import with_tempdir
 
 
 class TestDataBase(unittest.TestCase):

diff --git a/vunit/test/unit/test_dependency_graph.py → tests/unit/test_dependency_graph.py b/vunit/test/unit/test_dependency_graph.py → tests/unit/test_dependency_graph.py