Updated all Wishbone VCs and VCIs to comply with new standard

vunit/vhdl/verification_components/.vc/tb_wishbone_master_compliance_template.vhd

@@ -0,0 +1,71 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2020, Lars Asplund [email protected]
+
+library ieee;
+library osvvm;
+library vunit_lib;
+context vunit_lib.com_context;
+context vunit_lib.vunit_context;
+use ieee.std_logic_1164.all;
+use osvvm.randompkg.all;
+use vunit_lib.bus_master_pkg.all;
+use vunit_lib.check_pkg.all;
+use vunit_lib.com_types_pkg.all;
+use vunit_lib.log_levels_pkg.all;
+use vunit_lib.logger_pkg.all;
+use vunit_lib.queue_pkg.all;
+use vunit_lib.sync_pkg.all;
+use vunit_lib.vc_pkg.all;
+use vunit_lib.wishbone_pkg.all;
+
+entity tb_wishbone_master_compliance is
+  generic(
+    runner_cfg : string);
+end entity;
+
+architecture tb of tb_wishbone_master_compliance is
+
+  constant wishbone_master : wishbone_master_t := new_wishbone_master(
+    data_length => 32,
+    address_length => 32
+  );
+
+  signal clk : std_logic;
+  signal adr : std_logic_vector(31 downto 0);
+  signal dat_i : std_logic_vector(31 downto 0);
+  signal dat_o : std_logic_vector(31 downto 0);
+  signal sel : std_logic_vector(3 downto 0);
+  signal cyc : std_logic;
+  signal stb : std_logic;
+  signal we : std_logic;
+  signal stall : std_logic;
+  signal ack : std_logic;
+
+begin
+  -- DO NOT modify the test runner process.
+  test_runner : process
+  begin
+    test_runner_setup(runner, runner_cfg);
+    test_runner_cleanup(runner);
+  end process test_runner;
+
+  -- DO NOT modify the VC instantiation.
+  vc_inst: entity vunit_lib.wishbone_master
+    generic map(wishbone_master)
+    port map(
+      clk => clk,
+      adr => adr,
+      dat_i => dat_i,
+      dat_o => dat_o,
+      sel => sel,
+      cyc => cyc,
+      stb => stb,
+      we => we,
+      stall => stall,
+      ack => ack
+    );
+
+end architecture;

vunit/vhdl/verification_components/.vc/tb_wishbone_slave_compliance_template.vhd

@@ -0,0 +1,65 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2020, Lars Asplund [email protected]
+
+library ieee;
+library osvvm;
+library vunit_lib;
+context vunit_lib.com_context;
+context vunit_lib.vunit_context;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+use osvvm.randompkg.all;
+use vunit_lib.memory_pkg.all;
+use vunit_lib.sync_pkg.all;
+use vunit_lib.vc_pkg.all;
+use vunit_lib.wishbone_pkg.all;
+
+entity tb_wishbone_slave_compliance is
+  generic(
+    runner_cfg : string);
+end entity;
+
+architecture tb of tb_wishbone_slave_compliance is
+
+  constant memory : memory_t := new_memory;
+  constant wishbone_slave : wishbone_slave_t := new_wishbone_slave(
+    memory => memory
+  );
+
+  signal clk : std_logic;
+  signal adr    : std_logic_vector(31 downto 0) := (others => '0');
+  signal dat_i  : std_logic_vector(31 downto 0) := (others => '0');
+  signal dat_o  : std_logic_vector(31 downto 0) := (others => '0');
+  signal sel   : std_logic_vector(3 downto 0) := (others => '1');
+  signal cyc : std_logic;
+  signal stb : std_logic;
+  signal we : std_logic;
+  signal stall : std_logic;
+  signal ack : std_logic;
+
+begin
+  test_runner : process
+  begin
+    test_runner_setup(runner, runner_cfg);
+    test_runner_cleanup(runner);
+  end process test_runner;
+
+  vc_inst: entity vunit_lib.wishbone_slave
+    generic map(wishbone_slave)
+    port map(
+      clk => clk,
+      adr => adr,
+      dat_i => dat_i,
+      dat_o => dat_o,
+      sel => sel,
+      cyc => cyc,
+      stb => stb,
+      we => we,
+      stall => stall,
+      ack => ack
+    );
+
+end architecture;

vunit/vhdl/verification_components/.vc/wishbone_pkg/tb_wishbone_master_t_compliance_template.vhd

@@ -0,0 +1,34 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2020, Lars Asplund [email protected]
+
+library ieee;
+library vunit_lib;
+context vunit_lib.com_context;
+context vunit_lib.vunit_context;
+use ieee.std_logic_1164.all;
+use vunit_lib.bus_master_pkg.all;
+use vunit_lib.memory_pkg.all;
+use vunit_lib.sync_pkg.all;
+use vunit_lib.vc_pkg.all;
+use vunit_lib.wishbone_pkg.all;
+
+entity tb_wishbone_master_t_compliance is
+  generic(
+    runner_cfg : string);
+end entity;
+
+architecture tb of tb_wishbone_master_t_compliance is
+begin
+  test_runner : process
+    constant data_length : natural := 32;
+    constant address_length : natural := 32;
+
+    -- DO NOT modify this line and the lines below.
+  begin
+    test_runner_setup(runner, runner_cfg);
+    test_runner_cleanup(runner);
+  end process test_runner;
+end architecture;

vunit/vhdl/verification_components/.vc/wishbone_pkg/tb_wishbone_slave_t_compliance_template.vhd

@@ -0,0 +1,33 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2020, Lars Asplund [email protected]
+
+library ieee;
+library vunit_lib;
+context vunit_lib.com_context;
+context vunit_lib.vunit_context;
+use ieee.std_logic_1164.all;
+use vunit_lib.bus_master_pkg.all;
+use vunit_lib.memory_pkg.all;
+use vunit_lib.sync_pkg.all;
+use vunit_lib.vc_pkg.all;
+use vunit_lib.wishbone_pkg.all;
+
+entity tb_wishbone_slave_t_compliance is
+  generic(
+    runner_cfg : string);
+end entity;
+
+architecture tb of tb_wishbone_slave_t_compliance is
+begin
+  test_runner : process
+    constant memory : memory_t := new_memory;
+
+    -- DO NOT modify this line and the lines below.
+  begin
+    test_runner_setup(runner, runner_cfg);
+    test_runner_cleanup(runner);
+  end process test_runner;
+end architecture;

vunit/vhdl/verification_components/src/wishbone_master.vhd

@@ -17,14 +17,15 @@ use work.logger_pkg.all;
 use work.check_pkg.all;
 use work.log_levels_pkg.all;
 use work.sync_pkg.all;
+use work.wishbone_pkg.all;
+use work.vc_pkg.all;
 
 library osvvm;
 use osvvm.RandomPkg.all;
 
 entity wishbone_master is
   generic (
-    bus_handle : bus_master_t;
-    strobe_high_probability : real range 0.0 to 1.0 := 1.0
+    wishbone_master : wishbone_master_t
     );
   port (
     clk   : in std_logic;
@@ -41,10 +42,7 @@ entity wishbone_master is
 end entity;
 
 architecture a of wishbone_master is
-  constant rd_request_queue : queue_t := new_queue;
-  constant wr_request_queue : queue_t := new_queue;
   constant acknowledge_queue : queue_t := new_queue;
-  constant bus_ack_msg   : msg_type_t := new_msg_type("wb master ack msg");
   constant wb_master_ack_actor : actor_t := new_actor;
   signal start_cycle : std_logic := '0';
   signal end_cycle : std_logic := '0';
@@ -58,26 +56,25 @@ begin
     variable rnd : RandomPType;
   begin
     rnd.InitSeed(rnd'instance_name);
-    report rnd'instance_name;
+
     request_msg := null_msg;
     cycle_type := bus_read_msg;
     stb <= '0';
 
-    wait until rising_edge(clk);
     loop
-      receive(net, get_actor(bus_handle), request_msg);
+      receive(net, get_actor(wishbone_master), request_msg);
       msg_type := message_type(request_msg);
 
       if msg_type = bus_read_msg or msg_type = bus_write_msg then
         if msg_type /= cycle_type and cycle then
-          wait until not cycle; -- todo: is this necessary? the wb spec v4 does not explicitly forbid mixed cycles
+          wait until not cycle; -- TODO: is this necessary? the wb spec v4 does not explicitly forbid mixed cycles
           wait until rising_edge(clk);
         end if;
 
         start_cycle <= not start_cycle;
         cycle_type := msg_type;
 
-        while rnd.Uniform(0.0, 1.0) > strobe_high_probability loop
+        while rnd.Uniform(0.0, 1.0) > wishbone_master.p_strobe_high_probability loop
           wait until rising_edge(clk);
         end loop;
         adr <= pop_std_ulogic_vector(request_msg);
@@ -88,32 +85,27 @@ begin
           sel <= pop_std_ulogic_vector(request_msg);
         else
           we <= '0';
-          -- TODO why sel is not passed in msg for reading (present for writing)?
-          --sel <= pop_std_ulogic_vector(request_msg);
         end if;
         wait until rising_edge(clk) and stall = '0';
         stb <= '0';
 
         push(acknowledge_queue, request_msg);
 
-      elsif msg_type = wait_until_idle_msg then
+      elsif msg_type = wait_until_idle_msg or msg_type = wait_for_time_msg then
         if cycle then
           wait until not cycle;
         end if;
-        handle_wait_until_idle(net, msg_type, request_msg);
+        handle_sync_message(net, msg_type, request_msg);
 
       else
-        unexpected_msg_type(msg_type);
-
+        unexpected_msg_type(msg_type, get_std_cfg(wishbone_master));
       end if;
+
     end loop;
   end process;
 
   p_cycle : process
-    variable request_msg : msg_t;
-    variable ack_msg : msg_t;
     variable pending : natural := 0;
-    variable received_acks : natural := 0;
   begin
     cyc <= '0';
     cycle <= false;
@@ -140,7 +132,7 @@ begin
   end process;
 
   acknowledge : process
-    variable request_msg, reply_msg, ack_msg : msg_t;
+    variable request_msg, reply_msg : msg_t;
   begin
     wait until ack = '1' and rising_edge(clk);
     request_msg := pop(acknowledge_queue);