Added rule for locking

VUnit · Oct 27, 2024 · 3d92427 · 3d92427
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commit 3d92427
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diff --git a/docs/verification_components/user_guide.rst b/docs/verification_components/user_guide.rst
@@ -183,3 +183,10 @@ Rule 14
 All VCs shall support the sync interface.
 
 **Rationale**: Being able to verify whether a VC is idle and introduce delays between transactions is a common and useful feature for VC users.
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+Rule 15
+-------
+
+A VC shall keep the ``test_runner_cleanup`` phase entry gate locked while there are pending operations.
+
+**Rationale**: Locking the gate prevents the simulation from terminating prematurely.