WIP: Added support for Questa Visualizer.

tests/unit/test_modelsim_interface.py

@@ -328,7 +328,7 @@ def test_optimize(self, vsim_simulator_mixin_process, modelsim_process, check_ou
         write_file("file.vhd", "")
         project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("2008"))
         simif.compile_project(project)
-        config = make_config(sim_options={"modelsim.three_step_flow":True})
+        config = make_config(sim_options={"modelsim.three_step_flow": True})
 
         # First call should optimize design
         simif.simulate(self.simulation_output_path, "test_suite_name", config, False)
@@ -351,13 +351,14 @@ def test_optimize(self, vsim_simulator_mixin_process, modelsim_process, check_ou
         LOGGER.reset_mock()
         simif._optimized_designs[design_to_optimize]["optimized_design"] = None
         simif.simulate(self.simulation_output_path, "test_suite_name", config, False)
-        expected_calls = [
-            mock.call("Waiting for %s to be optimized.", design_to_optimize),
-            mock.call("Done waiting for %s to be optimized.", design_to_optimize),
+        expected_debug_calls = [mock.call("Waiting for %s to be optimized.", design_to_optimize)]
+        self.assertEqual(LOGGER.debug.call_count, len(expected_debug_calls))
+        LOGGER.debug.assert_has_calls(expected_debug_calls)
+        expected_error_calls = [
+            mock.call("Failed waiting for %s to be optimized (optimization failed).", design_to_optimize)
         ]
-        self.assertEqual(LOGGER.debug.call_count, len(expected_calls))
-        LOGGER.debug.assert_has_calls(expected_calls)
-
+        self.assertEqual(LOGGER.error.call_count, len(expected_error_calls))
+        LOGGER.error.assert_has_calls(expected_error_calls)
 
     def setUp(self):
         self.test_path = str(Path(__file__).parent / "test_modelsim_out")
@@ -382,6 +383,7 @@ def tearDown(self):
         if Path(self.test_path).exists():
             rmtree(self.test_path)
 
+
 def make_config(sim_options=None, generics=None, verilog=False):
     """
     Utility to reduce boiler plate in tests
@@ -400,4 +402,4 @@ def make_config(sim_options=None, generics=None, verilog=False):
     cfg.generics = {} if generics is None else generics
     cfg.vhdl_configuration_name = None
     cfg.vhdl_assert_stop_level = "error"
-    return cfg
+    return cfg