Merge pull request enjoy-digital#2122 from acceleratedtech/accelerate…

…d/uart-dynamic-baudrate-for-upstream feat: add uart_with_dynamic_baudrate to SoCCore
VOGL-electronic · Nov 15, 2024 · 8399c91 · 8399c91
2 parents 2b3fd72 + f53178d
commit 8399c91
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Showing 3 changed files with 10 additions and 9 deletions.
diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
@@ -202,14 +202,14 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
     else:
         return stream.SyncFIFO([("data", 8)], depth, buffered=True)
 
-def UARTPHY(pads, clk_freq, baudrate):
+def UARTPHY(pads, clk_freq, baudrate, with_dynamic_baudrate=False):
     # FT245 Asynchronous FIFO mode (baudrate ignored)
     if hasattr(pads, "rd_n") and hasattr(pads, "wr_n"):
         from litex.soc.cores.usb_fifo import FT245PHYAsynchronous
         return FT245PHYAsynchronous(pads, clk_freq)
     # RS232
     else:
-        return  RS232PHY(pads, clk_freq, baudrate)
+        return  RS232PHY(pads, clk_freq, baudrate, with_dynamic_baudrate=with_dynamic_baudrate)
 
 class UART(LiteXModule, UARTInterface):
     def __init__(self, phy=None,

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
@@ -1511,7 +1511,7 @@ def add_identifier(self, name="identifier", identifier="LiteX SoC", with_build_t
         self.add_config(name, identifier)
 
     # Add UART -------------------------------------------------------------------------------------
-    def add_uart(self, name="uart", uart_name="serial", uart_pads=None, baudrate=115200, fifo_depth=16):
+    def add_uart(self, name="uart", uart_name="serial", uart_pads=None, baudrate=115200, fifo_depth=16, with_dynamic_baudrate=False):
         # Imports.
         from litex.soc.cores.uart import UART, UARTCrossover
 
@@ -1550,7 +1550,7 @@ def add_uart(self, name="uart", uart_name="serial", uart_pads=None, baudrate=115
 
         # Crossover + UARTBone.
         elif uart_name in ["crossover+uartbone"]:
-            self.add_uartbone(baudrate=baudrate)
+            self.add_uartbone(baudrate=baudrate, with_dynamic_baudrate=with_dynamic_baudrate)
             uart = UARTCrossover(**uart_kwargs)
 
         # JTAG UART.
@@ -1588,7 +1588,7 @@ def add_uart(self, name="uart", uart_name="serial", uart_pads=None, baudrate=115
         # Regular UART.
         else:
             from litex.soc.cores.uart import UARTPHY
-            uart_phy  = UARTPHY(uart_pads, clk_freq=self.sys_clk_freq, baudrate=baudrate)
+            uart_phy  = UARTPHY(uart_pads, clk_freq=self.sys_clk_freq, baudrate=baudrate, with_dynamic_baudrate=with_dynamic_baudrate)
             uart      = UART(uart_phy, **uart_kwargs)
 
         # Add PHY/UART.
@@ -1604,15 +1604,15 @@ def add_uart(self, name="uart", uart_name="serial", uart_pads=None, baudrate=115
             self.add_constant("UART_POLLING", check_duplicate=False)
 
     # Add UARTbone ---------------------------------------------------------------------------------
-    def add_uartbone(self, name="uartbone", uart_name="serial", clk_freq=None, baudrate=115200, cd="sys"):
+    def add_uartbone(self, name="uartbone", uart_name="serial", clk_freq=None, baudrate=115200, cd="sys", with_dynamic_baudrate=False):
         # Imports.
         from litex.soc.cores import uart
 
         # Core.
         if clk_freq is None:
             clk_freq = self.sys_clk_freq
         self.check_if_exists(name)
-        uartbone_phy = uart.UARTPHY(self.platform.request(uart_name), clk_freq, baudrate)
+        uartbone_phy = uart.UARTPHY(self.platform.request(uart_name), clk_freq, baudrate, with_dynamic_baudrate=with_dynamic_baudrate)
         uartbone     = uart.UARTBone(
             phy           = uartbone_phy,
             clk_freq      = clk_freq,

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
@@ -100,6 +100,7 @@ def __init__(self, platform, clk_freq,
         uart_name                = "serial",
         uart_baudrate            = 115200,
         uart_fifo_depth          = 16,
+        uart_with_dynamic_baudrate = False,
 
         # Timer parameters.
         with_timer               = True,
@@ -255,11 +256,11 @@ def __init__(self, platform, clk_freq,
 
         # Add UARTBone.
         if with_uartbone:
-            self.add_uartbone(baudrate=uart_baudrate)
+            self.add_uartbone(baudrate=uart_baudrate, fifo_depth=uart_fifo_depth, with_dynamic_baudrate=with_dynamic_baudrate)
 
         # Add UART.
         if with_uart:
-            self.add_uart(name="uart", uart_name=uart_name, baudrate=uart_baudrate, fifo_depth=uart_fifo_depth)
+            self.add_uart(name="uart", uart_name=uart_name, baudrate=uart_baudrate, fifo_depth=uart_fifo_depth, with_dynamic_baudrate=uart_with_dynamic_baudrate)
 
         # Add JTAGBone.
         if with_jtagbone: