Formatting

[Schottkyc137]

This commit adds the initial infrastructure for formatting a VHDL file.

What the formatter is capable of

• Format any language element with a fixed configuration
• Preserve comments
• Preserve whitespaces in certain situations

What is still lacking for a feature complete formatter

• Configurations / settings for different styles
• integration into the language server

In this PR, the vhdl_lang binary file has been extended to allow for the --format flag. When vhdl_lang is called like

$ vhdl_lang --format my_file.vhd

the tool will print the formatted content of my_file.vhd into standard out. It will also check that the code is syntactically equivalent before and after.
Formatting is tested using unit tests as well as integration test; checking that every VHDL file of the example project is formatted in a way that retains the syntax.

The initial skeleton is basically done. I want to do some more tests and smaller refactoring (e.g., to remove duplicated code and make some things more flexible), but other than that, the formatter is ready to be used.