Fixed RV64 regression tests / compressed instruction implementation.

UoB-HPC · Sep 17, 2024 · b4bd3a0 · b4bd3a0
1 parent e8cfa42
commit b4bd3a0
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Showing 2 changed files with 7 additions and 47 deletions.
diff --git a/src/lib/arch/riscv/InstructionMetadata.cc b/src/lib/arch/riscv/InstructionMetadata.cc
@@ -33,6 +33,10 @@ InstructionMetadata::InstructionMetadata(const cs_insn& insn)
   std::memcpy(operands, insn.detail->riscv.operands,
               sizeof(cs_riscv_op) * operandCount);
 
+  std::cerr << std::hex << (unsigned)encoding[0] << " " << (unsigned)encoding[1]
+            << " " << (unsigned)encoding[2] << " " << (unsigned)encoding[3]
+            << std::dec << std::endl;
+
   convertCompressedInstruction(insn);
   alterPseudoInstructions(insn);
 }
@@ -457,23 +461,6 @@ void InstructionMetadata::duplicateFirstOp() {
   operandCount = 3;
 }
 
-void InstructionMetadata::createMemOpPosOne() {
-  // Given register sequence {Op_a, imm, reg} return {Op_a, mem, _}
-  assert(operands[1].type == RISCV_OP_IMM &&
-         "Incorrect operand type when creating memory operand");
-  assert(operands[2].type == RISCV_OP_REG &&
-         "Incorrect operand type when creating memory operand");
-
-  cs_riscv_op temp;
-  temp.type = RISCV_OP_MEM;
-  temp.mem.base = operands[2].reg;
-  temp.mem.disp = operands[1].imm;
-
-  operands[1] = temp;
-
-  operandCount = 2;
-}
-
 void InstructionMetadata::convertCompressedInstruction(const cs_insn& insn) {
   if (insnLengthBytes_ != 2) {
     return;
@@ -533,9 +520,6 @@ void InstructionMetadata::convertCompressedInstruction(const cs_insn& insn) {
 
       opcode = Opcode::RISCV_LD;
 
-      // Create operand formatted like LD instruction
-      createMemOpPosOne();
-
       break;
     }
     case Opcode::RISCV_C_ADDI4SPN:
@@ -600,17 +584,12 @@ void InstructionMetadata::convertCompressedInstruction(const cs_insn& insn) {
 
       opcode = Opcode::RISCV_SD;
 
-      // Create operand formatted like SD instruction
-      createMemOpPosOne();
-
       break;
     }
     case Opcode::RISCV_C_SWSP: {
       // sw rs2, offset[7:2](x2)
       opcode = Opcode::RISCV_SW;
 
-      createMemOpPosOne();
-
       break;
     }
     case Opcode::RISCV_C_ADD:
@@ -642,9 +621,6 @@ void InstructionMetadata::convertCompressedInstruction(const cs_insn& insn) {
 
       opcode = Opcode::RISCV_LD;
 
-      // Create operand formatted like LD instruction
-      createMemOpPosOne();
-
       break;
     }
     case Opcode::RISCV_C_ADDI: {
@@ -678,8 +654,6 @@ void InstructionMetadata::convertCompressedInstruction(const cs_insn& insn) {
       // sd rs2 ′ , offset[7:3](rs1 ′)
 
       opcode = Opcode::RISCV_SD;
-      // Create operand formatted like SD instruction
-      createMemOpPosOne();
 
       break;
     }
@@ -728,25 +702,19 @@ void InstructionMetadata::convertCompressedInstruction(const cs_insn& insn) {
 
       opcode = Opcode::RISCV_LW;
 
-      createMemOpPosOne();
-
       break;
     }
     case Opcode::RISCV_C_FLDSP:
       // TODO RV32DC/RV64DC-only once RV32 implemented
       // fld rd, offset[8:3](x2)
       opcode = Opcode::RISCV_FLD;
 
-      createMemOpPosOne();
-
       break;
     case Opcode::RISCV_C_SW: {
       // sw rs2 ′, offset[6:2](rs1 ′)
 
       opcode = Opcode::RISCV_SW;
 
-      createMemOpPosOne();
-
       break;
     }
     case Opcode::RISCV_C_J:
@@ -793,8 +761,6 @@ void InstructionMetadata::convertCompressedInstruction(const cs_insn& insn) {
 
       opcode = Opcode::RISCV_LW;
 
-      createMemOpPosOne();
-
       break;
     case Opcode::RISCV_C_SRLI:
       // srli rd ′ , rd ′ , shamt[5:0]
@@ -881,26 +847,20 @@ void InstructionMetadata::convertCompressedInstruction(const cs_insn& insn) {
 
       opcode = Opcode::RISCV_FSD;
 
-      createMemOpPosOne();
-
       break;
     case Opcode::RISCV_C_FLD:
       // TODO rv64dc ONLY, make check for this once RV32 implemented
       // fld rd ′, offset[7:3](rs1 ′)
 
       opcode = Opcode::RISCV_FLD;
 
-      createMemOpPosOne();
-
       break;
     case Opcode::RISCV_C_FSDSP:
       // TODO rv64dc ONLY, make check for this once RV32 implemented
       // fsd rs2, offset[8:3](x2)
 
       opcode = Opcode::RISCV_FSD;
 
-      createMemOpPosOne();
-
       break;
     case Opcode::RISCV_C_SUBW:
       // TODO rv64 ONLY, make check for this once RV32 implemented

diff --git a/src/lib/arch/riscv/Instruction_address.cc b/src/lib/arch/riscv/Instruction_address.cc
@@ -17,22 +17,22 @@ span<const memory::MemoryAccessTarget> Instruction::generateAddresses() {
       isInstruction(InsnType::isAtomic)) {
     // Atomics
     // Metadata operands[2] corresponds to instruction sourceRegValues[1]
-    assert(metadata_.operands[2].type == RISCV_OP_REG &&
+    assert(metadata_.operands[2].type == RISCV_OP_MEM &&
            "metadata_ operand not of correct type during RISC-V address "
            "generation");
     address = sourceValues_[1].get<uint64_t>();
   } else if (isInstruction(InsnType::isLoad) &&
              isInstruction(InsnType::isAtomic)) {
     // Load reserved
     // Metadata operands[1] corresponds to instruction sourceRegValues[0]
-    assert(metadata_.operands[1].type == RISCV_OP_REG &&
+    assert(metadata_.operands[1].type == RISCV_OP_MEM &&
            "metadata_ operand not of correct type during RISC-V address "
            "generation");
     address = sourceValues_[0].get<uint64_t>();
   } else if (isInstruction(InsnType::isStore) &&
              isInstruction(InsnType::isAtomic)) {
     // Store conditional
-    assert(metadata_.operands[2].type == RISCV_OP_REG &&
+    assert(metadata_.operands[2].type == RISCV_OP_MEM &&
            "metadata_ operand not of correct type during RISC-V address "
            "generation");
     address = sourceValues_[1].get<uint64_t>();