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"Component=" text fields for simulation (#37); Verification missing m…
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lukasc-ubc committed Jan 2, 2018
1 parent 40946da commit 8774ee2
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Showing 6 changed files with 32 additions and 14 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
<prolog/>
<epilog/>
<doc/>
<autorun>true</autorun>
<autorun>false</autorun>
<autorun-early>false</autorun-early>
<shortcut/>
<show-in-menu>true</show-in-menu>
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
<autorun>false</autorun>
<autorun-early>false</autorun-early>
<shortcut/>
<show-in-menu>true</show-in-menu>
<show-in-menu>false</show-in-menu>
<group-name>Setup 2</group-name>
<menu-path>siepic_menu.simulation.begin</menu-path>
<interpreter>python</interpreter>
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2 changes: 1 addition & 1 deletion klayout_dot_config/pymacros/SiEPIC - General Library.lym
Original file line number Diff line number Diff line change
Expand Up @@ -175,7 +175,7 @@ class Waveguide(PCellDeclarationHelper):
text.halign=halign
shape = self.cell.shapes(LayerDevRecN).insert(text)
t = Trans(angle, False, pt2)
text = Text ('Lumerical_INTERCONNECT_component=ebeam_wg_integral_1550', t, 0.1/dbu, -1)
text = Text ('Component=ebeam_wg_integral_1550', t, 0.1/dbu, -1)
text.halign=halign
shape = self.cell.shapes(LayerDevRecN).insert(text)
t = Trans(angle, False, pt3)
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2 changes: 1 addition & 1 deletion klayout_dot_config/pymacros/SiEPIC - Test Environment.lym
Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ if 0:
[n.display() for n in nets]

# Verification
if 0:
if 1:
from SiEPIC import scripts

scripts.layout_check(verbose=True)
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6 changes: 5 additions & 1 deletion klayout_dot_config/python/SiEPIC/extend.py
Original file line number Diff line number Diff line change
Expand Up @@ -330,7 +330,7 @@ def print_parameter_values(self):
1) box on layer PinRec, indicating direction (out of component)
2) text on layer PinRec, inside the path
'''
def find_pins(self, verbose=False):
def find_pins(self, verbose=False, polygon_devrec=None):
from .core import Pin
from . import _globals
from .utils import get_technology
Expand Down Expand Up @@ -434,6 +434,8 @@ def find_pins_component(self, component):
p.component = component
return pins



'''
Components:
'''
Expand Down Expand Up @@ -513,6 +515,8 @@ def find_components(self, verbose=False, cell_selected=None):
library = text.string[len("Lumerical_INTERCONNECT_library="):]
if text.string.find("Lumerical_INTERCONNECT_component=") > -1:
component = text.string[len("Lumerical_INTERCONNECT_component="):]
if text.string.find("Component=") > -1:
component = text.string[len("Component="):]
if text.string.find("Spice_param:") > -1:
spice_params = text.string[len("Spice_param:"):]
iter2.next()
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32 changes: 23 additions & 9 deletions klayout_dot_config/python/SiEPIC/scripts.py
Original file line number Diff line number Diff line change
Expand Up @@ -626,7 +626,7 @@ def calculate_area():
# nets, components = topcell.identify_nets()
# selected_component = components[5] (elsewhere the desired component is selected)

def trim_netlist (nets, components, selected_component):
def trim_netlist (nets, components, selected_component, verbose=None):
selected = selected_component
#>17 <2
#nets[0].pins[0].component.idx
Expand All @@ -651,7 +651,8 @@ def trim_netlist (nets, components, selected_component):
if(selected.idx in net):
trimmed_components = [each for each in components if each.idx in net]
trimmed_nets = [each for each in nets if (each.pins[0].component.idx in net or each.pins[1].component.idx in net)]
print("success - netlist trimmed")
if verbose:
print("success - netlist trimmed")

return trimmed_nets, trimmed_components

Expand Down Expand Up @@ -707,7 +708,7 @@ def layout_check(cell = None, verbose=False):

# Waveguide checking
rdb_cell = next(rdb.each_cell())
rdb_cat_id_wg = rdb.create_category("Waveguide errors")
rdb_cat_id_wg = rdb.create_category("Waveguide")
rdb_cat_id_wg_path = rdb.create_category(rdb_cat_id_wg, "Path")
rdb_cat_id_wg_path.description = "Waveguide path: Only 2 points allowed in a path. Convert to a Waveguide if necessary."
rdb_cat_id_wg_radius = rdb.create_category(rdb_cat_id_wg, "Radius")
Expand All @@ -719,28 +720,34 @@ def layout_check(cell = None, verbose=False):

# Component checking
rdb_cell = next(rdb.each_cell())
rdb_cat_id_comp = rdb.create_category("Component errors")
rdb_cat_id_comp = rdb.create_category("Component")
rdb_cat_id_comp_flat = rdb.create_category(rdb_cat_id_comp, "Flattened component")
rdb_cat_id_comp_flat.description = "SiEPIC-Tools Verification, Netlist extraction, and Simulation only functions on hierarchical layouts, and not on flattened layouts. Add to the discussion here: https://github.com/lukasc-ubc/SiEPIC-Tools/issues/37"
rdb_cat_id_comp_overlap = rdb.create_category(rdb_cat_id_comp, "Overlapping component")
rdb_cat_id_comp_overlap.description = "Overlapping components (defined as overlapping DevRec layers; touch is ok)"

# Connectivity checking
rdb_cell = next(rdb.each_cell())
rdb_cat_id = rdb.create_category("Connectivity errors")
rdb_cat_id = rdb.create_category("Connectivity")
rdb_cat_id_discpin = rdb.create_category(rdb_cat_id, "Disconnected pin")
rdb_cat_id_discpin.description = "Disconnected pin"
rdb_cat_id_mismatchedpin = rdb.create_category(rdb_cat_id, "Mismatched pin")
rdb_cat_id_mismatchedpin.description = "Mismatched pin widths"

# Simulation checking
rdb_cell = next(rdb.each_cell())
rdb_cat_id = rdb.create_category("Simulation")
rdb_cat_id_sim_nomodel = rdb.create_category(rdb_cat_id, "Missing compact model")
rdb_cat_id_sim_nomodel.description = "A compact model for this component was not found. Possible reasons: 1) Please run SiEPIC | Simulation | Setup Lumerical INTERCONNECT and CML, to make sure that the Compact Model Library is installed in INTERCONNECT, and that KLayout has a list of all component models. 2) the library does not have a compact model for this component. "

# Design for Test checking
from SiEPIC.utils import load_DFT
DFT=load_DFT()
if DFT:
if verbose:
print(DFT)
rdb_cell = next(rdb.each_cell())
rdb_cat_id = rdb.create_category("Design for Test errors")
rdb_cat_id = rdb.create_category("Design for test")
rdb_cat_id_optin_unique = rdb.create_category(rdb_cat_id, "opt_in label: same")
rdb_cat_id_optin_unique.description = "Automated test opt_in labels should be unique."
rdb_cat_id_optin_missing = rdb.create_category(rdb_cat_id, "opt_in label: missing")
Expand Down Expand Up @@ -838,10 +845,16 @@ def layout_check(cell = None, verbose=False):
if gc_orientation_error:
if verbose:
print( " - Found DFT error, GC facing the wrong way: %s, %s" % (c.component, c.trans.angle) )
polygon = c.polygon
rdb_item = rdb.create_item(rdb_cell.rdb_id(),rdb_cat_id_GCorient.rdb_id())
rdb_item.add_value(pya.RdbItemValue( polygon.to_dtype(dbu) ) )
rdb_item.add_value(pya.RdbItemValue( c.polygon.to_dtype(dbu) ) )

# Pre-simulation check: do components have models?
if not c.has_model():
if verbose:
print( " - Missing compact model, for component: %s" % (c.component) )
rdb_item = rdb.create_item(rdb_cell.rdb_id(),rdb_cat_id_sim_nomodel.rdb_id())
rdb_item.add_value(pya.RdbItemValue( c.polygon.to_dtype(dbu) ) )


if DFT:
# DFT verification
Expand All @@ -854,7 +867,8 @@ def layout_check(cell = None, verbose=False):
# opt_in labels
for ti1 in range(0,len(opt_in)):
t = opt_in[ti1]['Text']
box = pya.Box(t.x-2*t.size, t.y-2*t.size, t.x+2*t.size, t.y+2*t.size)
box_s = 1000
box = pya.Box(t.x-box_s, t.y-box_s, t.x+box_s, t.y+box_s)
# opt_in labels check for unique
for ti2 in range(ti1+1, len(opt_in)):
if opt_in[ti1]['opt_in'] == opt_in[ti2]['opt_in']:
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